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19-4593; Rev 0; 7/09
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
General Description
The MAX5965A/MAX5965B are quad, monolithic, -48V power controllers designed for use in IEEE(R) 802.3af-compliant/pre-IEEE 802.3at-compatible power-sourcing equipment (PSE). These devices provide powered device (PD) discovery, classification, current limit, DC and AC load disconnect detections in compliance with the IEEE 802.3af standard. The MAX5965A/MAX5965B are pin compatible with the MAX5952/MAX5945/LTC4258/LTC4259A PSE controllers and provide additional features. The MAX5965A/MAX5965B feature a high-power mode that provides up to 45W per port. The MAX5965A/ MAX5965B provide new Class 5 and 2-event classification (Class 6) for detection and classification of highpower PDs. The MAX5965A/MAX5965B provide instantaneous readout of each port current through the I2C interface. The MAX5965A/MAX5965B also provide high-capacitance detection for legacy PDs. These devices feature an I2C-compatible, 3-wire serial interface, and are fully software configurable and programmable. The class-overcurrent detection function enables system power management to detect if a PD draws more than the allowable current. The MAX5965A/MAX5965B's extensive programmability enhances system flexibility, enables field diagnosis, and allows for uses in other applications. The MAX5965A/MAX5965B provide four operating modes to suit different system requirements. Auto mode allows the devices to operate automatically without any software supervision. Semi-automatic mode automatically detects and classifies a device connected to a port after initial software activation, but does not power up that port until instructed to by software. Manual mode allows total software control of the device and is useful for system diagnostics. Shutdown mode terminates all activities and securely turns off power to the ports. The MAX5965A/MAX5965B provide input undervoltage lockout (UVLO), input undervoltage detection, a loadstability safety check during detection, input overvoltage lockout, overtemperature detection, output voltage slew-rate limit during startup, power-good status, and fault status. The MAX5965A/MAX5965B's programmability includes startup timeout, overcurrent timeout, and load-disconnect detection timeout. The MAX5965A/MAX5965B are available in a 36-pin SSOP package and are rated for both extended (-40C to +85C) and upper commercial (0C to +85C) temperature ranges.
Features
o IEEE 802.3af Compliant/Pre-IEEE 802.3at Compatible o Instantaneous Readout of Port Current Through I2C Interface o High-Power Mode Enables Up to 45W Per Port o High-Capacitance Detection for Legacy Devices o Pin Compatible with MAX5952/MAX5945/ LTC4258/LTC4259A o Four Independent Power-Switch Controllers o PD Detection and Classification (Including 2Event Classification) o Load-Stability Safety Check During Detection o Supports Both DC and AC Load Removal Detections o I2C-Compatible, 3-Wire Serial Interface o Current Foldback and Duty-Cycle-Controlled Current Limit o Open-Drain INT Signal o Direct Fast Shutdown Control Capability o Special Class 5 Classification
MAX5965A/MAX5965B
Ordering Information
PART MAX5965AEAX+ MAX5965AUAX+* MAX5965BEAX+ MAX5965BUAX+* TEMP RANGE -40C to +85C 0C to +85C -40C to +85C 0C to +85C PIN-PACKAGE 36 SSOP 36 SSOP 36 SSOP 36 SSOP
+Denotes a lead(Pb)-free/RoHS-compliant package. *Future product--contact factory for availability.
Selector Guide
PART MAX5965AEAX+ MAX5965AUAX+ MAX5965BEAX+ MAX5965BUAX+ PIN-PACKAGE 36 SSOP 36 SSOP 36 SSOP 36 SSOP AC DISCONNECT FEATURE No No Yes Yes
Applications
Power-Sourcing Equipment (PSE) Switches/Routers Midspan Power Injectors
Pin Configuration appears at end of data sheet.
IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to VEE, unless otherwise noted.) AGND, DGND, DET_, VDD, RESET, A3-A0, SHD_, OSC, SCL, SDAIN, AUTO .............................................-0.3V to +80V OUT_........................................................-12V to (AGND + 0.3V) GATE_ (internally clamped) (Note 1) ..................-0.3V to +11.4V SENSE_ ..................................................................-0.3V to +24V VDD, RESET, MIDSPAN, A3-A0, SHD_, OSC, SCL, SDAIN and AUTO to DGND ..................................-0.3V to +7V INT and SDAOUT to DGND....................................-0.3V to +12V Maximum Current into INT, SDAOUT, DET_ .......................80mA Maximum Power Dissipation (TA = +70C) 36-Pin SSOP (derate 17.4mW/C above +70C) .....1388.9mW Operating Temperature Ranges: MAX5965A/MAX5965B_EAX ........................-40C to +85C MAX5965A/MAX5965B_UAX ...............................0C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: GATE_ is internally clamped to 11.4V above VEE. Driving GATE_ higher than 11.4V above VEE may damage the device.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAGND = 32V to 60V, VEE = 0V, VDD to VDGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = +48V, VDGND = +48V, VDD = (VDGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.) (Note 2)
PARAMETER POWER SUPPLIES VAGND Operating Voltage Range VDGND VDD VDD to VDGND, VDGND = VAGND VDD to VDGND, VDGND = VEE VOUT_ = VEE, VSENSE_ = VEE, DET_ = AGND, all logic inputs open, SCL = SDAIN = VDD. INT and SDAOUT unconnected. Measured at AGND in power mode after GATE_ pullup All logic inputs high, measured at VDD Power mode, gate drive on, VGATE = VEE (Note 3) SHD_ = DGND, VGATE_ = VEE + 10V VSENSE = 600mV, VGATE_ = VEE + 2V VGATE - VEE, power mode, gate drive on, IPU = 1A 9 VAGND - VEE 32 0 2.4 3.0 60 60 3.6 3.6 V SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Currents
IEE
4.8
6.8
mA
IDIG GATE DRIVER AND CLAMPING GATE_ Pullup Current Weak GATE_ Pulldown Current Maximum Pulldown Current External Gate Drive IPU IPDW IPDS VGS
0.2
0.4
-40
-50 42 100 10
-65
A A mA
11.5
V
2
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
ELECTRICAL CHARACTERISTICS (continued)
(VAGND = 32V to 60V, VEE = 0V, VDD to VDGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = +48V, VDGND = +48V, VDD = (VDGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.) (Note 2)
PARAMETER CURRENT LIMIT IVEE = 00 Maximum VSENSE_ allowed during current limit, VOUT_ = 0V (ICUT = 000) (Note 4) IVEE = 01 IVEE = 10 IVEE = 11 ICUT = 000 (Class 0/3) ICUT =110 (Class 1) Overcurrent Threshold After Startup Overcurrent VSENSE_ threshold allowed for t tFAULT after startup; VOUT_ = 0V, (IVEE = 00) ICUT = 111 (Class 2) ICUT = 001 ICUT = 010 ICUT = 011 ICUT = 100 ICUT =101 ICUT = 000, ICUT = 110, ICUT = 111 ICUT = 001...101 202 192 186 170 177 47 86 265 310 355 398 443 212 202 190 180 186 55 94 280 327 374 419 466 32 V 13 220 212 mV 200 190 196 64 101 mV 295 345 395 440 488 SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5965A/MAX5965B
Current-Limit Clamp Voltage
VSU_LIM
VFLT_LIM
Foldback Initial OUT_ Voltage
VFLBK_ST
VOUT_ - VEE, above which the current-limit trip voltage starts folding back, IVEE = 00
Foldback Final OUT_ Voltage Minimum Foldback Current-Limit Threshold SENSE_ Input Bias Current
IVEE = 00, ICUT = 000, VOUT - VEE above VFLBK_END which the current-limit trip voltage reaches VTH_FB VTH_FB VOUT_ = AGND = 60V, IVEE = 00, ICUT = 000 VSENSE_ = VEE -5
50
V
64 +5
mV A
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3
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
ELECTRICAL CHARACTERISTICS (continued)
(VAGND = 32V to 60V, VEE = 0V, VDD to VDGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = +48V, VDGND = +48V, VDD = (VDGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.) (Note 2)
PARAMETER SUPPLY MONITORS VEE Undervoltage Lockout VEE Undervoltage Lockout Hysteresis VEE Overvoltage Lockout VEE Overvoltage Lockout Hysteresis VEE Undervoltage VDD Overvoltage VDD Undervoltage VDD Undervoltage Lockout VDD Undervoltage Lockout Hysteresis Thermal Shutdown Threshold VEEUVLO VEEUVLOH VEE_OV VOVH VEE_UV VDD_OV VDD_UV VDDUVLO VDDHYS Ports shut down and device resets if its junction temperature exceeds this limit, temperature increasing (Note 5) Thermal hysteresis, temperature decreasing (Note 5) VOUT = AGND, all modes OUT_ discharge current, detection and classification off, port shutdown, VOUT_ = AGND - 2.8V VOUT_ - VEE, OUT_ decreasing Minimum time PGOOD has to be high to set bit in register 10h 200 1.5 2.0 220 3 VEE_UV event bit is set if AGND - VEE < VEE_UV, VEE increasing VDD_OV event bit is set if VDD - VDGND > VDD_OV; VDD increasing VDD_UV is set if VDD - VDGND > VDD_UV, VDD decreasing Device operates when VDD - DGND > VDDUVLO, VDD increasing AGND - VEE, AGND - VEE increasing Ports shut down if AGND - VEE < VUVLO VEEUVLOH VEE_OV event bit sets and ports shut down if AGND - VEE > VEE_OV, AGND increasing 28.5 3 62.5 1 40 3.82 2.7 2 120 V V V V V V V V mV SYMBOL CONDITIONS MIN TYP MAX UNITS
TSHD
+150
C
Thermal Shutdown Hysteresis OUTPUT MONITOR OUT_ Input Current Idle Pullup Current at OUT_ PGOOD High Threshold PGOOD Hysteresis PGOOD Low-to-High Glitch Filter
TSHDH
20
C
IBOUT IDIS PGTH PGHYS tPGOOD
2 265 2.5
A A V mV ms
4
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
ELECTRICAL CHARACTERISTICS (continued)
(VAGND = 32V to 60V, VEE = 0V, VDD to VDGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = +48V, VDGND = +48V, VDD = (VDGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.) (Note 2)
PARAMETER LOAD DISCONNECT DC Load Disconnect Threshold AC Load Disconnect Threshold Oscillator Buffer Gain OSC Fail Threshold OSC Input Impedance Load Disconnect Timer DETECTION Detection Probe Voltage (First Phase) Detection Probe Voltage (Second Phase) Current-Limit Protection VDPH1 VDPH2 IDLIM AGND - VDET_ during the first detection phase AGND - VDET_ during the second detection phase VDET_ = AGND, during detection, measure current through DET_ If AGND - VOUT < VDCP after the first detection phase a short circuit to AGND is detected First point measurement current threshold for open condition (Note 9) Detection rejects lower values Detection rejects higher values VAGND - VDET_ during classification DET_ = AGND, during classification Class 0, Class 1 Classification Current Thresholds ICL Classification current thresholds between classes Class 1, Class 2 Class 2, Class 3 Class 3, Class 4 Class 4, Class 5 32 16 68 5.5 13 21 31 45 6.5 14.5 23 33 48 20 80 7.5 16 25 35 51 mA 19.0 3.8 9.0 1.5 4 9.3 1.8 4.2 9.6 2.2 V V mA VDCTH Minimum VSENSE allowed before disconnect (DC disconnect active), VOUT_ = 0V Current into DET_, for I < IACTH the port powers off, ACD_EN_ bit = H; VOSC_IN = 2.2V, MAX5965B (Note 6) VDET_/VOSC, ACD_EN_ bit = H, MAX5965B Port does not power on if VOSC < VOSC_FAIL and ACD_EN_ bit is high, MAX5965B (Note 7) OSC input impedance when all the ACD_EN_ are active, MAX5965B Time from VSENSE < VDCTH to gate shutdown (Note 8) 2.5 3.75 5.0 mV SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5965A/MAX5965B
IACTH AOSC VOSC_FAIL ZOSC tDISC
285 2.9 1.8 100 300
320 3.0
360 3.1 2.2
A V/V V k
400
ms
Short-Circuit Threshold
VDCP
1
V
Open-Circuit Threshold Resistor Detection Window Resistor Rejection Window CLASSIFICATION Classification Probe Voltage Current-Limit Protection
ID_OPEN RDOK RDBAD
12.5 26.5 15.2
A k k
VCL ICILIM
V mA
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5
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
ELECTRICAL CHARACTERISTICS (continued)
(VAGND = 32V to 60V, VEE = 0V, VDD to VDGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = +48V, VDGND = +48V, VDD = (VDGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.) (Note 2)
PARAMETER Digital Input Low Digital Input High Internal Input Pullup/Pulldown Resistor Open-Drain Output Low Voltage Digital Input Leakage Open-Drain Leakage TIMING Startup Time tSTART Time during which a current limit set by VSU_LIM is allowed, starts when the GATE_ is turned on (Note 9) Maximum allowed time for an overcurrent condition set by VFLT_LIM after startup (Note 9) Minimum delay between any port turning off, does not apply in case of a reset Time allowed for the port voltage to reset before detection starts tDET tDMID tCLASS tDLY Time allowed for classification Time VAGND must be above the VEEUVLO thresholds before the device operates RSTR bits = 00 Time a port has to wait before turning on after an overcurrent fault during normal operation, RSTR_EN_ bits = high RSTR bits = 01 RSTR bits = 10 RSTR bits = 11 Watchdog Clock Period ADC PERFORMANCE Resolution Range LSB Step Size Integral Nonlinearity (Relative) INL 9 0.51 1 0.2 1.5 Bits V mV LSB tWD Rate of decrement of the watchdog timer 2 16 x tFAULT 32 x tFAULT 64 x tFAULT 0 164 ms ms Maximum time allowed before detection is completed 2.0 19 50 60 70 ms SYMBOL VIL VIH RDIN VOL IDL IOL Pullup (pulldown) resistor to VDD (DGND) to set default level ISINK = 15mA Input connected to the pull voltage Open-drain high impedance, VOUT_ = 3.3V 2.4 25 50 75 0.4 2 2 CONDITIONS MIN TYP MAX 0.9 UNITS V V k V A A
DIGITAL INPUTS/OUTPUTS (Referred to DGND)
Fault Time
tFAULT
50
60
70
ms
Port Turn-Off Time Detection Reset Time Detection Time Midspan Mode Detection Delay Classification Time VEEUVLO Turn-On Delay
tOFF
0.5 80 90 330 2.4 23 4
ms ms ms s ms ms
Restart Timer
tRESTART
6
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
ELECTRICAL CHARACTERISTICS (continued)
(VAGND = 32V to 60V, VEE = 0V, VDD to VDGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = +48V, VDGND = +48V, VDD = (VDGND + 3.3V), TA = +25C. Currents are positive when entering the pin and negative otherwise.) (Note 2)
PARAMETER Differential Nonlinearity Gain Error ADC Absolute Accuracy Serial-Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time for a START Condition Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition (Sr) Data Hold Time Data in Setup Time Rise Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting Setup Time for STOP Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed fSCL tBUF tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT tR tF tSU, STO CB tSP 1.2 0.6 1.2 0.6 0.6 100 100 20 + 0.1CB 20 + 0.1CB 0.6 400 50 300 300 300 VSENSE = 300mV 295 300 SYMBOL DNL CONDITIONS MIN TYP 0.2 MAX 1.5 3 305 400 UNITS LSB % LSB kHz s s s s s ns ns ns ns s pF ns
MAX5965A/MAX5965B
TIMING CHARACTERISTICS (For 2-Wire Fast Mode)
Limits to TA = -40C are guaranteed by design. Default values. The charge/discharge currents are programmable through the serial interface (see the Register Map and Description section). Note 4: Default values. The current-limit thresholds are programmed through the I2C-compatible serial interface (see the Register Map and Description section). Note 5: Functional test is performed over thermal shutdown entering test mode. Note 6: This is the default value. Threshold can be programmed through serial interface R23h[2:0]. Note 7: AC disconnect works only if (VDD - VDGND) 3V and DGND is connected to AGND. Note 8: tDISC can also be programmed through the serial interface (R16H) (see the Register Map and Description section). Note 9: RD = (VOUT_2 - VOUT_1)/(IDET_2 - IDET_1). VOUT_1, VOUT_2, IDET_2, and IDET_1 represent the voltage at OUT_ and the current at DET_ during phase 1 and 2 of the detection. Note 10: Default values. The startup and fault times can also be programmed through the I2C serial interface (see the Register Map and Description section). Note 2: Note 3:
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7
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Typical Operating Characteristics
(VEE = -48V, VDD = +3.3V, VAUTO = VAGND = VDGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, IVEE = 00, ICUT = 000, TA = +25C, all registers = default setting, unless otherwise noted.)
ANALOG SUPPLY CURRENT vs. INPUT VOLTAGE
MAX5965A toc01
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX5965A toc02
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
MEASURED AT VDD VDD = 3.6V
MAX5965A toc03
5.5 5.4 5.3 SUPPLY CURRENT (mA) 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 32
MEASURED AT AGND
5.5 5.4 5.3 SUPPLY CURRENT (mA) 5.2 5.1 5.0 4.9 4.8 4.7 4.6 VEE = -32V 4.5 VEE = -60V VEE = -48V
130 125 SUPPLY CURRENT (FA) 120 115 110 105
VDD = 3.3V
VDD = 2.4V 100 60 85 -40 -15 10 35 60 85
36
40
44
48
52
56
60
-40
-15
10
35
VAGND - VEE (V)
TEMPERATURE (NC)
TEMPERATURE (NC)
DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE
MEASURED AT VDD
MAX5965A toc04
VEE UNDERVOLTAGE LOCKOUT vs. TEMPERATURE
MAX5965A toc05
GATE OVERDRIVE vs. INPUT VOLTAGE
10.08 10.06 GATE OVERDRIVE (V) 10.04 10.02 10.00 9.98 9.96 9.94 9.92 9.90
MAX5965A toc06
130 125 SUPPLY CURRENT (FA) 120 115 110 105 100
30.0 UNDERVOLTAGE LOCKOUT (V) 29.5 29.0 28.5 28.0 27.5 27.0
10.10
2.4
2.6
2.8
3.0
3.2
3.4
3.6
-40
-15
10
35
60
85
32
36
40
44
48
52
56
60
SUPPLY VOLTAGE (V)
TEMPERATURE (NC)
VAGND - VEE (V)
GATE OVERDRIVE vs. TEMPERATURE
MAX5965A toc07
SENSE TRIP VOLTAGE vs. TEMPERATURE
MAX5965A toc08
SENSE TRIP VOLTAGE vs. INPUT VOLTAGE
188.5 SENSE TRIP VOLTAGE (mV) 188.0 187.5 187.0 186.5 186.0 185.5
MAX5965A toc09
10.20 10.15 10.10 GATE OVERDRIVE (V) 10.05 10.00 9.95 9.90 9.85 9.80 -40 -15 10 35 60
196
189.0
SENSE TRIP VOLTAGE (mV)
192
188
184
85
180
-40
-15
10
35
60
85
185.0
32
36
40
44
48
52
56
60
TEMPERATURE (NC)
TEMPERATURE (NC)
VAGND - VEE (V)
8
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Typical Operating Characteristics (continued)
(VEE = -48V, VDD = +3.3V, VAUTO = VAGND = VDGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, IVEE = 00, ICUT = 000, TA = +25C, all registers = default setting, unless otherwise noted.)
FOLDBACK CURRENT-LIMIT THRESHOLD vs. OUTPUT VOLTAGE
MAX5965A toc10
MAX5965A/MAX5965B
FOLDBACK CURRENT-LIMIT THRESHOLD vs. OUTPUT VOLTAGE
MAX5965A toc10A
DC LOAD DISCONNECT THRESHOLD vs. TEMPERATURE
DC LOAD DISCONNECT THRESHOLD (mV)
MAX5965A toc11
300 250 VSENSE - VEE (mV) 200 150 100 50 0
500 450 400 VSENSE - VEE (mV) 350 300 250 200 150 100 50 0 ICUT = 001 ICUT = 001
6
5
4
3
2 0 10 20 30 40 50 VOUT - VEE (V)
0
10
20
30
40
50
-40
-15
10
35
60
85
VOUT - VEE (V)
TEMPERATURE (NC)
OVERCURRENT TIMEOUT (RLOAD = 240 TO 57)
MAX5965A toc12
OVERCURRENT RESPONSE WAVEFORM (MAX5965AUAX) (RLOAD = 240 TO 57)
(AGND - VOUT) 50V/div 0V IOUT 200mA/div 0A VGATE_ 10V/div VEE INT 5V/div 0A VEE 0V 400s/div GATE 10V/div INT 2V/div
MAX5965A toc13
(AGND - VOUT) 50V/div 0V IOUT 200mA/div
0V 20ms/div
SHORT-CIRCUIT RESPONSE TIME
MAX5965A toc14
SHORT-CIRCUIT RESPONSE TIME
MAX5965A toc15
(AGND - VOUT) 20V/div 0V
(AGND - VOUT) 20V/div 0V
0A
IOUT 200mA/div
IOUT 10A/div 130mA VGATE_ 10V/div VEE 4s/div
VEE 20ms/div
VGATE_ 10V/div
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9
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Typical Operating Characteristics (continued)
(VEE = -48V, VDD = +3.3V, VAUTO = VAGND = VDGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, IVEE = 00, ICUT = 000, TA = +25C, all registers = default setting, unless otherwise noted.)
RESET TO OUT TURN-OFF DELAY ZERO-CURRENT DETECTION WAVEFORM
MAX5965A toc17
MAX5965A toc16
RESET 2V/div 0V
(AGND - VOUT) 20V/div 0V IOUT 200mA/div 0A VGATE_ 10V/div VEE INT 2V/div 0V 100ms/div
IOUT 200mA/div 0A VGATE 5V/div VEE
OVERCURRENT RESTART DELAY
MAX5965A toc18
STARTUP WITH VALID PD (25kI AND 0.1F)
MAX5965A toc19
(AGND - VOUT) 20V/div 0V IOUT 200mA/div 0A 0A VGATE_ 10V/div VEE 400ms/div 0V
VAGND - VOUT 20V/div
IOUT 100mA/div
VGATE 5V/div VEE
DETECTION WITH INVALID PD (25kI AND 10F)
DETECTION WITH INVALID PD (15k)
MAX5965A toc21
MAX5965A toc20
VAGND - VOUT 20V/div 0V IOUT 1mA/div 0A VGATE 10V/div VEE 0A
(AGND - VOUT) 5V/div 0V
IOUT 1mA/div
100ms/div
10
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Typical Operating Characteristics (continued)
(VEE = -48V, VDD = +3.3V, VAUTO = VAGND = VDGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, IVEE = 00, ICUT = 000, TA = +25C, all registers = default setting, unless otherwise noted.)
STARTUP IN MIDSPAN MODE WITH VALID PD (25kI AND 0.1F)
MAX5965A/MAX5965B
DETECTION WITH INVALID PD (33k)
MAX5965A toc22
MAX5965A toc23
(AGND - VOUT) 5V/div 0V 0V
VAGND - VOUT 20V/div
IOUT 100mA/div 0A IOUT 1mA/div 0A VGATE 5V/div VEE 100ms/div
DETECTION WITH MIDSPAN MODE WITH INVALID PD (15k)
MAX5965A toc24
DETECTION WITH MIDSPAN MODE WITH INVALID PD (33k)
MAX5965A toc25
(AGND - VOUT) 5V/div 0V
(AGND - VOUT) 5V/div 0V
0A
IOUT 1mA/div VGATE_ 10V/div 400ms/div
0A
IOUT 1mA/div VGATE_ 10V/div 400ms/div
VEE
VEE
OUTPUT SHORTED
DETECTION WITH INVALID PD (OPEN CIRCUIT, USING TYPICAL OPERATING CIRCUIT 1)
MAX5965A toc26 MAX5965A toc27
0V
VAGND - VOUT 5V/div IOUT 1mA/div
0V
(AGND - VOUT) 5V/div
0A
0A
IOUT 1mA/div
VEE
VGATE 10V/div
VEE
VGATE_ 10V/div 40ms/div
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11
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Typical Operating Characteristics (continued)
(VEE = -48V, VDD = +3.3V, VAUTO = VAGND = VDGND = 0V, RESET = SHD_ = unconnected, RSENSE = 0.5, IVEE = 00, ICUT = 000, TA = +25C, all registers = default setting, unless otherwise noted.)
DETECTION WITH INVALID PD (OPEN CIRCUIT, USING TYPICAL OPERATING CIRCUIT 2)
MAX5965A toc28
STARTUP WITH DIFFERENT PD CLASSES
MAX5965A toc29
0V
(AGND - VOUT) 5V/div
VAGND - VOUT 5V/div
0A
IOUT 1mA/div
0V CLASS 5 CLASS 4 CLASS 3 CLASS 2 CLASS 1 IOUT 20mA/div
VEE
VGATE_ 10V/div 40ms/div
0A
2-EVENT CLASSIFICATION WITH A CLASS 4 PD
MAX5965A toc30
VAGND - VOUT 5V/div 0V IOUT 0A VEE 20mA/div VGATE 10V/div
Pin Description
PIN 1 NAME RESET FUNCTION Hardware Reset. Pull RESET low for at least 300s to reset the device. All internal registers reset to their default value. The address (A0-A3), and AUTO and MIDSPAN input-logic levels latch on during low-tohigh transition of RESET. RESET is internally pulled up to VDD with a 50k resistor. Midspan Mode Input. An internal 50k pulldown resistor to DGND sets the default mode to endpoint PSE operation (power-over-signal pairs). Pull MIDSPAN to VDIG to set midspan operation. The MIDSPAN value latches after the device is powered up or reset (see the PD Detection section). Open-Drain Interrupt Output. INT goes low whenever a fault condition exists. Reset the fault condition using software or by pulling RESET low (see the Interrupt section for more information about interrupt management). Serial Interface Clock Line Input Serial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the Typical Operating Circuits). Connect SDAOUT to SDAIN if using a 2-wire, I2C-compatible system.
2
MIDSPAN
3 4 5
INT SCL SDAOUT
12
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Pin Description (continued)
PIN 6 NAME SDAIN FUNCTION Serial Interface Input Data Line. Connect the data line optocoupler output to SDAIN (see the Typical Operating Circuits). Connect SDAIN to SDAOUT if using a 2-wire, I2C-compatible system. Address Bits. A3-A0 form the lower part of the device's address. Address inputs default high with an internal 50k pullup resistor to VDD. The address values latch when VDD or VEE ramps up and exceeds its UVLO threshold or after a reset. The 3 MSBs of the address are set to 010. Detection/Classification Voltage Outputs. Use DET1 to set the detection and classification probe voltages on port 1. Use DET1 for the AC voltage sensing of port 1 when using the AC disconnect scheme (see the Typical Operating Circuits). Digital Ground. Connect to digital ground. Positive Digital Supply. Connect to a digital power supply (reference to DGND). Port Shutdown Inputs. Pull SHD_ low to turn off the external FET on port_. Internally pulled up to VDD with a 50k resistor. Analog Ground. Connect to the high-side analog supply. MOSFET Source Current-Sense Negative Inputs. Connect to the source of the power MOSFET and connect a current-sense resistor between SENSE_ and VEE (see the Typical Operating Circuits).
MAX5965A/MAX5965B
7-10
A3-A0
11-14 15 16 17- 20 21 22, 25, 29, 32
DET1-DET4 DGND VDD SHD1-SHD4 AGND SENSE4, SENSE3, SENSE2, SENSE1 GATE4, GATE3, GATE2, GATE1
23, 26, 30, 33
Port_ MOSFET Gate Drivers. Connect GATE_ to the gate of the external MOSFET (see the Typical Operating Circuits).
24, 27, 31, 34 28
MOSFET Drain-Output Voltage Senses. Connect OUT_ to the power MOSFET drain through a resistor OUT4, OUT3, (100 to 100k). The low leakage at OUT_ limits the drop across the resistor to less than 100mV (see the OUT2, OUT1 Typical Operating Circuits). VEE Low-Side Analog Supply Input. Connect the low-side analog supply to VEE (-48V). Bypass with a 1F capacitor between AGND and VEE. Auto or Shutdown Mode Input. Force AUTO high to enter auto mode after a reset or power-up. Drive low to put the MAX5965A/MAX5965B into shutdown mode. In shutdown mode, software controls the operational modes of the MAX5965A/MAX5965B. A 50k internal pulldown resistor defaults to AUTO low. AUTO latches when VDD or VEE ramps up and exceeds its UVLO threshold or when the device resets. Software commands can take the MAX5965A/MAX5965B out of AUTO while AUTO is high. Oscillator Input. AC-disconnect detection function uses OSC. Connect a 100Hz 10%, 2VP-P 5%, +1.2V offset sine wave to OSC. If the oscillator positive peak falls below the OSC_FAIL threshold of 2V, the ports that have the AC function enabled shut down and are not allowed to power-up. When not using the ACdisconnect detection function, leave OSC unconnected.
35
AUTO
36
OSC
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Functional Diagram
VDD SCL SDAIN SDAOUT SHD_ OSC_IN DGND CURRENT SENSING THREE-WIRE SERIAL PORT INTERFACE A0 DETECTION/ CLASSIFICATION SM PORT STATE MACHINE (SM) ACD_ENABLE 50A A=3 GATE_ AUTO PWR_EN MIDSPAN CENTRAL LOGIC UNIT (CLU) RESET REGISTER FILE DGND VDD AC DISCONNECT SIGNAL (ACD) 13V CLAMP AC DETECTION* 9-BIT ADC CONVERTER 10V A2 REGISTER FILE A3 VOLTAGE SENSING OUT_ OSCILLATOR MONITOR VOLTAGE PROBING AND CURRENT-LIMIT CONTROL DET_
A1
FAST DISCHARGE CONTROL
100mA 90A MAX
INT
ACD REFERENCE CURRENT SENSE_
CURRENT MEASUREMENT 9-BIT ADC CURRENT LIMIT (ILIM) CURRENT-LIMIT DETECTOR
AGND
ANALOG BIAS/ SUPPLY MONITOR
+10V ANALOG +5V DIG VOLTAGE REFERENCES CURRENT REFERENCES
VEE
OPEN CIRCUIT (OC)
OVERCURRENT (OVC)
FOLDBACK CONTROL
MAX5965A/MAX5965B
4mV
182mV
212mV
*AC DETECTION ONLY FOR THE MAX5965B.
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Detailed Description
The MAX5965A/MAX5965B are quad -48V power controllers designed for use in IEEE 802.3af-compliant/preIEEE 802.3at-compatible PSE. The devices provide PD discovery, classification, current limit, DC and AC load disconnect detections in compliance with the IEEE 802.3af standard. The MAX5965A/MAX5965B are pin compatible with the MAX5952/MAX5945/LTC4258/LTC4259A PSE controllers and provides additional features. The MAX5965A/MAX5965B feature a high-power mode, which provides up to 45W per port. The devices allow the user to program the current-limit and overcurrent thresholds up to 2.5 times the default thresholds. The MAX5965A/MAX5965B can also be programmed to decrease the current-limit and overcurrent threshold by 15% for high operating voltage conditions to keep the output power constant. The MAX5965A/MAX5965B provide new Class 5 and 2event classification (Class 6) for detection and classification of high-power PDs. The MAX5965A/MAX5965B provide instantaneous readout of each port current through the I2C interface. The MAX5965A/MAX5965B also provide high-capacitance detection for legacy PDs. The MAX5965A/MAX5965B are fully software configurable and programmable through an I2C-compatible, 3-wire serial interface with 49 registers. The class-overcurrent detection function enables system power management to detect if a PD draws more than the allowable current. The MAX5965A/MAX5965B's extensive programmability enhances system flexibility, enables field diagnosis, and allows for uses in other applications. The MAX5965A/MAX5965B provide four operating modes to suit different system requirements. Auto mode allows the device to operate automatically without any software supervision. Semi-auto mode automatically detects and classifies a device connected to a port after initial software activation but does not power up that port until instructed to by software. Manual mode allows total software control of the device and is useful for system diagnostics. Shutdown mode terminates all activities and securely turns off power to the ports. The MAX5965A/MAX5965B provide input undervoltage lockout, input undervoltage detection, a load-stability safety check during detection, input overvoltage lockout, overtemperature detection, output voltage slew-rate limit during startup, power-good, and fault status. The MAX5965A/MAX5965B's programmability includes startup timeout, overcurrent timeout, and load-disconnect detection timeout. The MAX5965A/MAX5965B communicate with the system microcontroller through an I2C-compatible interface. The MAX5965A/MAX5965B feature separate input and output data lines (SDAIN and SDAOUT) for use with optocoupler isolation. As slave devices, the MAX5965A/MAX5965B include four address inputs allowing 16 unique addresses. A separate INT output and four independent shutdown inputs (SHD_) provide fast response from a fault to port shutdown between the MAX5965A/MAX5965B and the microcontroller. A RESET input allows hardware reset of the device.
MAX5965A/MAX5965B
Reset
Reset is a condition the MAX5965A/MAX5965B enter after any of the following conditions: 1) After power-up (V EE and V DD rise above their UVLO thresholds). 2) Hardware reset. The RESET input is driven low and back high again any time after power-up. 3) Software reset. Writing a 1 into R1Ah[4] any time after power-up. 4) Thermal shutdown. During a reset, the MAX5965A/MAX5965B reset their register map to the reset state as shown in Table 37 and latch in the state of AUTO (pin 35) and MIDSPAN (pin 2). During normal operation, change at the AUTO and MIDSPAN input is ignored. While the condition that caused the reset persists (i.e. high temperature, RESET input low, or UVLO conditions) the MAX5965A/ MAX5965B do not acknowledge any addressing from the serial interface.
Port Reset (R1Ah[3:0])
Set high anytime during normal operation to turn off power and clear the events and status registers of the corresponding port. Port reset only resets the events and status registers.
Midspan Mode
In midspan mode, the device adopts cadence timing during the detection phase. When cadence timing is enabled and a failed detection occurs, the port waits between 2s and 2.4s before attempting to detect again. Midspan mode is activated by setting R11[1] high. The status of the MIDSPAN pin is written to R11[1] during power-up or after a reset. MIDSPAN is internally pulled low by a 50k resistor.
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Operation Modes
The MAX5965A/MAX5965B contain four independent, but identical state machines to provide reliable and realtime control of the four network ports. Each state machine has four operating modes: auto mode, semiauto mode, manual, and shutdown. Auto mode allows the device to operate automatically without any software supervision. Semi-auto mode, upon request, continuously detects and classifies a device connected to a port but does not power up that port until instructed by software. Manual mode allows total software control of the device and is useful in system diagnostics. Shutdown mode terminates all activities and securely turns off power to the ports. Switching between auto, semi, or manual mode does not interfere with the operation of the port. When the port is set into shutdown mode, all the port operations are immediately stopped and the port remains idle until shutdown is exited. R14h[DET_EN_, CLASS_EN_] default to low in semi-auto mode. Use software to set R14h[DET_EN_, CLASS_EN_] to high to start the detection and/or classification routines. R14h[DET_EN_, CLASS_EN_] are reset every time the software commands a power off of the port (either through reset or PWR_OFF). In any other case, the status of the bits is left unchanged (including when the state machine turns off the power because a load disconnect or a fault condition is encountered).
Automatic (Auto) Mode Enter automatic (auto) mode by forcing the AUTO input high prior to a reset, or by setting R12h[P_M1,P_M0] to [1,1] during normal operation (see Tables 16a and 16b). In auto mode, the MAX5965A/MAX5965B performs detection, classification, and power up the port automatically once a valid PD is detected at the port. If a valid PD is not connected at the port, the MAX5965A/MAX5965B repeat the detection routine continuously until a valid PD is connected.
Going into auto mode, the DET_EN and CLASS_EN bits are set to high and stay high unless changed by software. Using software to set DET_EN and/or CLASS_EN low causes the MAX5965A/MAX5965B to skip detection and/or classification. As a protection, disabling the detection routine in auto mode does not allow the corresponding port to power up, unless the DET_BY (R23H[4]) is set to 1. The AUTO status is latched into the register only during a reset. Any changes to the AUTO input after reset are ignored.
Manual Mode Enter manual mode by setting R12h[P_M1,P_M0] to [0,1] during normal operation (see Tables 16a and 16b). Manual mode allows the software to dictate any sequence of operation. Write a 1 to both R14h[DET_EN_] and R14h[CLASS_EN_] to start detection and classification operations, respectively, and in that priority order. After execution, the command is cleared from the register(s). PWR_ON_ has highest priority. Setting PWR_ON_ high at any time causes the device to immediately enter the powered mode. Setting DET_EN and CLASS_EN high at the same time causes detection to be performed first. Once in the powered state, the device ignores DET_EN_ or CLASS_EN_ commands. When switching to manual mode from another mode, DET_EN_, CLASS_EN_ default to low. These bits become pushbutton rather than configuration bits (i.e., writing ones to these bits while in manual mode commands the device to execute one cycle of detection and/or classification. The bits are reset back to zeros at the end of the execution). Shutdown Mode Enter shutdown mode by forcing the AUTO input low prior to a reset, or by setting R12h[P_M1,P_M0] to [0,0] during normal operation (see Tables 16a and 16b). Putting the MAX5965A/MAX5965B into shutdown mode immediately turns off power and halts all operations to the corresponding port. The event and status bits of the affected port(s) are also cleared. In shutdown mode, the DET_EN_, CLASS_EN_, and PWR_ON_ commands are ignored. In shutdown mode, the serial interface operates normally.
Semi-Automatic (Semi-Auto) Mode Enter semi-auto mode by setting R12h[P_M1,P_M0] to [1,0] during normal operation (see Tables 16a and 16b). In semi-auto mode, the MAX5965A/MAX5965B, upon request, perform detection and/or classification repeatedly but do not power up the port(s), regardless of the status of the port connection. Setting R19h[PWR_ON_] (Table 22) high immediately terminates detection/classification routines and turns on power to the port(s).
16
PD Detection
When PD detection is activated, the MAX5965A/ MAX5965B probe the output for a valid PD. After each detection cycle, the device sets the DET_END_ bit R04h/05h[3:0] high and reports the detection results in the status registers R0Ch[2:0], R0Dh[2:0], R0Eh[2:0], and R0Fh[2:0]. The DET_END_ bit is reset to low when read through R05h or after a port reset.
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
A valid PD has a 25k discovery signature characteristic as specified in the IEEE 802.3af/at standard. Table 1 shows the IEEE 802.3af/at specification for a PSE detecting a valid PD signature. See the Typical Operating Circuits and Figure 1a (Detection, Classification, and Power-Up Port Sequence). The MAX5965A/MAX5965B can probe and categorize different types of devices connected to the port such as: a valid PD, an open circuit, a low resistive load, a high resistive load, a high capacitive load, a positive DC supply, or a negative DC supply. During detection, the MAX5965A/MAX5965B keep the external MOSFET off and force two probe voltages through the DET_ input. The current through the DET_ input is measured as well as the voltage at OUT_. A two-point slope measurement is used as specified by the IEEE 802.3af standard to verify the device connected to the port. The MAX5965A/MAX5965B implement appropriate settling times and a 100ms digital integration to reject 50Hz/60Hz power-line noise coupling. An external diode, in series with the DET_ input, restricts PD detection to the first quadrant as specified by the IEEE 802.3af/at standard. To prevent damage to non-PD devices, and to protect themselves from an output short circuit, the MAX5965A/MAX5965B limit the current into DET_ to less than 2mA maximum during PD detection. In midspan mode, the MAX5965A/MAX5965B wait 2.2s before attempting another detection cycle after every failed detection. The first detection, however, happens immediately after issuing the detection command.
MAX5965A/MAX5965B
High-Capacitance Detection The CLC_EN bit in register R23h[5] enables the large capacitor detection feature for legacy PD devices. When CLC_EN = 1, the high-capacitance detection limit is extended up to 150F. CLC_EN = 0 is the default condition for the normal capacitor size detection. See Table 1 and the Register Map and Description section.
Table 1. PSE PI Detection Modes Electrical Requirement (Table 33-2 of the IEEE 802.3af Standard)
PARAMETER Open-Circuit Voltage Short-Circuit Current Valid Test Voltage Voltage Difference Between Test Points Time Between Any Two Test Points Slew Rate Accept Signature Resistance Reject Signature Resistance Open-Circuit Resistance Accept Signature Capacitance Reject Signature Capacitance Signature Offset Voltage Tolerance Signature Offset Current Tolerance SYMBOL VOC ISC VVALID VTEST tBP VSLEW RGOOD RBAD ROPEN CGOOD CBAD VOS IOS 19 < 15 500 -- 10 0 0 MIN -- -- 2.8 1 2 MAX 30 5 10 -- -- 0.1 26.5 > 33 -- 150 -- 2.0 12 UNITS V mA V V ms V/s k k k nF F V A This timing implies a 500Hz maximum probing frequency ADDITIONAL INFORMATION In detection mode only In detection mode only
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Powered Device Classification (PD Classification)
During the PD classification mode, the MAX5965A/ MAX5965B force a probe voltage (-18V) at DET_ and measure the current into DET_. The measured current determines the class of the PD. After each classification cycle, the device sets the CL_END_ bit (R04h/05h[7:4]) high and reports the classification results in the status registers R0Ch[6:4], R0Dh[6:4], R0Eh[6:4], and R0Fh[6:4]. The CL_END_ bit is reset to low when read through register R05h or after a port reset. Both status registers, R04h, and R05h are cleared after the port powers down. Table 2 shows the IEEE 802.3af requirement for a PSE classifying a PD at the power interface (PI). The MAX5965A/MAX5965B support high power beyond the IEEE 802.3af standard by providing additional classifications (Class 5 and 2-event classification). voltage at -9V. The EN_CL6 bits in R1Ch[7:4] enable 2event classification on a per port basis.
Powered State
When the MAX5965A/MAX5965B enter a powered state, the tSTART and tDISC timers are reset. Before turning on the port power, the MAX5965A/MAX5965B check if any other port is not turning on and if the tFAULT timer is zero. Another check is performed if the ACD_EN bit is set, in this case the OSC_FAIL bit must be low (oscillator is okay) for the port to be powered. If these conditions are met, the MAX5965A/MAX5965B enter startup where it turns on power to the port. An internal signal, POK_, asserts high when VOUT is within 2V from VEE. PGOOD_ status bits are set high if POK_ stays high longer than tPGOOD. PGOOD immediately resets when POK goes low (see Figure 2). The PG_CHG_ bit sets when a port powers up or down. PWR_EN sets when a port powers up and resets when a port shuts down. The port shutdown timer lasts 0.5ms and prevents other ports from turning off during that period, except in the case of emergency shutdowns (RESET = L, RESET_IC = H, VEEUVLO, VDDUVLO, and TSHD). The MAX5965A/MAX5965B always check the status of all ports before turning off. A priority logic system determines the order to prevent the simultaneous turn-on or turn-off of the ports. The port with the lesser ordinal number gets priority over the others (i.e., port 1 turns on first, port 2 second, port 3 third, and port 4 fourth). Setting PWR_OFF_ high turns off power to the corresponding port.
Class 5 PD Classification During classification, if the MAX5965A/MAX5965B detect currents in excess of ICLASS > 48mA, then the PD will be classified as a Class 5 powered device. Status registers R0Ch[6:4] or R0Dh[6:4] or R0Eh[6:4] or R0Fh[6:4] will report the Class 5 classification result. 2-Event (Class 6) PD Classification When 2-event classification is activated, the classification cycle is repeated three times with 8ms wait time between each cycle (see Figure 1b). Between each classification cycle, the MAX5965A/MAX5965B do not reset the port voltage completely but keeps the output
Table 2. PSE Classification of a PD (Table 33-4 of the IEEE 802.3af)
MEASURED ICLASS (mA) 0 to 5 > 5 and < 8 8 to 13 > 13 and < 16 16 to 21 > 21 and < 25 25 to 31 > 31 and < 35 35 to 45 > 45 and < 51 51 to 68 Class 0 May be Class 0 and 1 Class 1 May be Class 1 or 2 Class 2 May be Class 2 or 3 Class 3 May be Class 3 or 4 Class 4 May be Class 4 or 5 Class 5 CLASSIFICATION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
80ms 0V 150ms tDETI 150ms tDETII 21.3ms tCLASS t
0V
-4V
-9V
OUT_
-18V
-48V
Figure 1a. Detection, Classification, and Power-Up Port Sequence
80ms 0
150ms tDETI
150ms tDETII
21.3ms tCLASSI
8ms
21.3ms tCLASSII
8ms
21.3ms tCLASSIII t
0V
-4V
-9V
OUT_
-18V
-48V
Figure 1b. Detection, 2-Event Classification, and Power-Up Port Sequence
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
After power-off due to an overcurrent fault, and if the RSTR_EN bit is set, the tFAULT timer is not immediately reset but starts decrementing at the same slower pace. The MAX5965A/MAX5965B allow the port to be powered on only when the tFAULT counter is at zero. This feature sets an automatic duty-cycle protection to the external MOSFET avoiding overheating. The MAX5965A/MAX5965B continuously flag when the current exceeds the maximum current allowed for the class as indicated in the CLASS status register. When class overcurrent occurs, the MAX5965A/MAX5965B set the IVC bit in register R09h.
POK
tPGOOD
PGOOD
ICUT Register and High-Power Mode
ICUT Register The ICUT register determines the maximum current limits allowed for each port of the MAX5965A/MAX5965B. The 3 ICUT bits (R2Ah[6:4], R2Ah[2:0], R2Bh[6:4], and R2Bh[2:0]) allow programming of the current-limit and overcurrent thresholds in excess of the IEEE standard limit (see Tables 34a, 34b, and 34c). The ICUT registers can be written to directly through the I2C interface when CL_DISC (R17h[2]) is set to 0 (see Table 3). In this case, the current limit of the port is configured regardless of the status of the classification.
By setting the CL_DISC bit to 1, the MAX5965A/ MAX5965B automatically set the ICUT register based upon the classification result of the port. See Table 3 and the Register Map and Description section.
Figure 2. PGOOD Timing
Overcurrent Protection
A sense resistor RS connected between SENSE_ and VEE monitors the load current. Under normal operating conditions, the voltage across RS (VRS) never exceeds the threshold V SU_LIM . If V RS exceeds V SU_LIM , an internal current-limiting circuit regulates the GATE voltage, limiting the current to ILIM = VSU_LIM/RS. During transient conditions, if VRS exceeds VSU_LIM by more than 1V, a fast pulldown circuit activates to quickly recover from the current overshoot. During startup, if the current-limit condition persists, when the startup timer, t START, times out, the port shuts off, and the STRT_FLT_ bit is set. In the normal powered state, the MAX5965A/MAX5965B check for overcurrent conditions as determined by VFLT_LIM = ~88% of VSU_LIM. The tFAULT counter sets the maximum allowed continuous overcurrent period. The tFAULT counter increases when VRS exceeds VFLT_LIM and decreases at a slower pace when VRS drops below VFLT_LIM. A slower decrement for the tFAULT counter allows for detecting repeated short-duration overcurrents. When the counter reaches the t FAULT limit, the MAX5965A/MAX5965B power off the port and assert the IMAX_FLT_ bit. For a continuous overstress, a fault latches exactly after a period of tFAULT. VSU_LIM is programmable through the ICUT registers R2Ah[6:4], R2Ah[2:0], R2Bh[6:4], R2Bh[2:0], and the IVEE bits in register R29h[1:0]. See the High-Power Mode section for more information on the ICUT register.
High-Power Mode When CL_DISC (R17h[2]) is set to 0, high-power mode is configured by setting the ICUT bits to any combination other than 000, 110, or 111 (note that 000 is the default value for the IEEE standard limit). See Table 3 and the Register Map and Description section.
Foldback Current
During startup and normal operation, an internal circuit senses the voltage at OUT_ and reduces the currentlimit value when (VOUT_ - VEE) > 28V. The foldback function helps to reduce the power dissipation on the FET. The current limit eventually reduces down to 1/3 of ILIM when (VOUT_ - VEE ) > 48V (see Figure 3a). For high-power mode, the foldback starts when (VOUT_ VEE ) > 10V (see Figure 3b). In high-power mode, the current limit (ILIM) is reduced down to minimum foldback current (VTH_FB/RS) when (VOUT_ - VEE ) > 48V.
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Table 3. Automatic ICUT Programming
CL_DISC 0 1 1 1 1 1 1 1 1 1 1 1 1 PORT CLASSIFICATION ENx_CL6 EN_HP_ALL EN_HP_CL6 EN_HP_CL5 RESULT Any 1 2 0, 3 4, 5 5 5 4 4 6 or Illegal 6 or Illegal 6 or Illegal 6 or Illegal X X X X X X X X X 0 1 1 1 X X X X 0 1 1 1 1 X 1 1 0 X X X X X X X X X X 1 0 X X X X X X 1 0 x X X X X X EN_HP_CL4 X X X X X X X 1 0 X X X X RESULTING ICUT REGISTER BITS User programmed ICUT = 110 ICUT = 111 ICUT = 000 ICUT = 000 ICUT = R24h[6:4] ICUT = 000 ICUT = R24h[6:4] ICUT = 000 -- (See Table 35a) ICUT = 000 ICUT = 000
MAX5965A/MAX5965B
MOSFET Gate Driver
Connect the gate of the external n-channel MOSFET to GATE_. An internal 50A current source pulls GATE_ to (VEE + 10V) to turn on the MOSFET. An internal 40A current source pulls down GATE_ to VEE to turn off the MOSFET. The pullup and pulldown current controls the maximum slew rate at the output during turn-on or turn-off. Use the following equation to set the maximum slew rate: VOUT IGATE = t CGD
where CGD is the total capacitance between GATE and DRAIN of the external MOSFET. Current limit and the capacitive load at the drain control the slew rate during startup. During current-limit regulation, the MAX5965A/MAX5965B manipulate the GATE_ voltage to control the voltage at SENSE_ (VRS). A fast pulldown activates if V RS overshoots the limit threshold (VSU_LIM). The fast pulldown current increases with the amount of overshoot. The maximum fast pulldown current is 100mA. During turn-off, when the GATE voltage reaches a value lower than 1.2V, a strong pulldown switch is activated to keep the MOSFET securely off.
(VRS - VEE) VSU_LIM
(VRS - VEE) VSU_LIM
VSU_LIM / 3
VTH_FB
28V
48V
(VOUT_ - VEE)
10V
48V
(VOUT_ - VEE)
Figure 3a. Foldback Current Characteristics
Figure 3b. Foldback Current Characteristics for High-Power Mode
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Digital Logic
VDD supplies power for the internal logic circuitry. VDD ranges from +3.0V to +5.5V and determines the logic thresholds for the CMOS connections (SDAIN, SDAOUT, SCL, AUTO, SHD_, A_). This voltage range enables the MAX5965A/MAX5965B to interface with a nonisolated low-voltage microcontroller. The MAX5965A/MAX5965B check the digital supply for compatibility with the internal logic. The MAX5965A/MAX5965B also feature a VDD undervoltage lockout (VDDUVLO) of +2.0V. A VDDUVLO condition keeps the MAX5965A/MAX5965B in reset and the ports shut off. Bit 0 in the supply event register shows the status of VDDUVLO (Table 12) after VDD has recovered. All logic inputs and outputs reference to DGND. For AC-disconnected detection, DGND and AGND must be connected together externally. Connect DGND to AGND at a single point in the system as close as possible to the MAX5965A/MAX5965B. 60V. The digital supply also contains an undervoltage lockout (VDDUVLO). The MAX5965A/MAX5965B also feature three other undervoltage and overvoltage interrupts: VEE undervoltage interrupt (VEEUV), VDD undervoltage interrupt (V DDUV ), and V DD overvoltage interrupt (VDDOV). A fault latches into the supply events register (Table 12), but the MAX5965A/MAX5965B does not shut down the ports with VEEUV, VDDUV, or VDDOV.
DC Disconnect Monitoring
Setting R13h[DCD_EN_] bits high enables DC load monitoring during a normal powered state. If VRS (the voltage across RS) falls below the DC load disconnect threshold, VDCTH, for more than tDISC, the device turns off power and asserts the LD_DISC_ bit of the corresponding port.
AC Disconnect Monitoring (MAX5965A/MAX5965B)
The MAX5965A/MAX5965BB feature AC load disconnect monitoring. Connect an external sine wave to OSC. The oscillator requirements are: 1) VP-P x Frequency = 200VP-P x Hz 15% 2) Positive peak voltage > +2.2V 3) Frequency > 60Hz A 100Hz 10%, 2VP-P 5%, with +1.3V offset (VPEAK = +2.3V typical) is recommended. The MAX5965A/MAX5965BB buffer and amplify three times the external oscillator signal and sends the signal to DET_, where the sine wave is AC-coupled to the output. The MAX5965A/MAX5965BB sense the presence of the load by monitoring the amplitude of the AC current returned to DET_ (see the Functional Diagram). Setting R13h[ACD_EN_] bits high enable AC load disconnect monitoring during a normal powered state. If the AC current peak at the DET_ input falls below IACTH for more than tDISC, the device turns off power and asserts the LD_DISC_ bit of the corresponding port. IACTH is programmable using R23h[0-3]. An internal comparator checks for a proper amplitude of the oscillator input. If the positive peak of the input sinusoid falls below a safety value of 2V (typ), OSC_FAIL sets and the port shuts down. Power cannot be applied to the ports when ACD_EN is set high and OSC_FAIL is set high. Leave OSC unconnected or connect it to DGND when not using AC-disconnect detection.
Hardware Shutdown
SHD_ shuts down the respective ports without using the serial interface. Hardware shutdown offers an emergency turn-off feature that allows a fast disconnect of the power supply from the port. Pull SHD_ low to remove power. SHD_ also resets the corresponding events and status register bits.
Interrupt
The MAX5965A/MAX5965B contain an open-drain logic output (INT) that goes low when an interrupt condition exists. R00h and R01h (Tables 6 and 7) contain the definitions of the interrupt registers. The mask register R01h determines events that trigger an interrupt. As a response to an interrupt, the controller reads the status of the event register to determine the cause of the interrupt and takes subsequent actions. Each interrupt event register also contains a Clear on Read (CoR) register. Reading through the CoR register address clears the interrupt. INT remains low when reading the interrupt through the readonly addresses. For example, to clear a startup fault on the port 4 read address 09h (see Table 11). Use the global pushbutton bit in register 1Ah (bit 7, Table 23) to clear interrupts, or use a software or hardware reset.
Undervoltage and Overvoltage Protection
The MAX5965A/MAX5965B contain several undervoltage and overvoltage protection features. Table 12 in the Register Map and Description section shows a detailed list of the undervoltage and overvoltage protection features. An internal VEE undervoltage lockout (VEEUVLO) circuit keeps the MOSFET off and the MAX5965A/ MAX5965B in reset until VAGND - VEE exceeds 29V for more than 3ms. An internal VEE overvoltage (VEE_OV) circuit shuts down the ports when (VAGND - VEE) exceeds
22
Thermal Shutdown
If the MAX5965A/MAX5965B die temperature reaches +150C, an overtemperature fault generates and the MAX5965A/MAX5965B shut down. The MOSFETs turn off. The die temperature of the MAX5965A/MAX5965B must cool down below +130C to remove the overtemperature fault condition. After a thermal shutdown, the part is reset.
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Watchdog
The R1Dh, R1Eh, and R1Fh registers control the watchdog operation. The watchdog function, when enabled, allows the MAX5965A/MAX5965B to gracefully take over control or securely shuts down the power to the ports in case of software/firmware crashes. Contact the factory for more details.
I2C-Compatible Serial Interface
The MAX5965A/MAX5965B operate as a slave that sends and receives data through an I2C-compatible, 2wire or 3-wire interface. The interface uses a serial-data input line (SDAIN), a serial-data output line (SDAOUT), and a serial-clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and from the MAX5965A/MAX5965B, and generates the SCL clock that synchronizes the data transfer. In most applications, connect the SDAIN and the SDAOUT lines together to form the serial-data line (SDA). Using the separate input and output data lines allows optocoupling with the controller bus when an isolated supply powers the microcontroller. The MAX5965A/MAX5965B SDAIN line operates as an input. The MAX5965A/MAX5965B SDAOUT operates as an open-drain output. A pullup resistor, typically 4.7k, is required on SDAOUT. The MAX5965A/MAX5965B SCL line operates only as an input. A pullup resistor, typically 4.7k, is required on SCL if there are multiple masters, or if the master in a single-master system has an opendrain SCL output.
MAX5965A/MAX5965B
Address Inputs
A3, A2, A1, and A0 represent the 4 LSBs of the chip address. The complete chip address is 7 bits (see Table 4). The 4 LSBs latch on the low-to-high transition of RESET or after a power-supply start (either on VDD or VEE). Address inputs default high through an internal 50k pullup resistor to VDD. The MAX5965A/MAX5965B also respond to the call through a global address 30h (see the Global Addressing and Alert Response Protocol section).
Table 4. MAX5965A/MAX5965B Address
0 1 0 A3 A2 A1 A0 R/W
SDAIN tBUF tSU, DAT tLOW tHD, DAT tSU, STA tHD, STA tSU, STO
SCL tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 4. 2-Wire, Serial-Interface Timing Details
SDAIN/SDA tBUF tSU, DAT tLOW tHD, DAT tSU, STA tHD, STA
tSU, STO
SCL tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 5. 3-Wire, Serial-Interface Timing Details
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Serial Addressing Each transmission consists of a START condition (Figure 6) sent by a master, followed by the MAX5965A/ MAX5965B 7-bit slave address plus R/W bit, a register address byte, one or more data bytes, and finally a STOP condition. START and STOP Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master finishes communicating with the slave, the master issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The STOP condition frees the bus for another transmission. Bit Transfer Each clock pulse transfers one data bit (Figure 7). The data on SDA must remain stable while SCL is high. Acknowledge The acknowledge bit is a clocked 9th bit (Figure 8) that the recipient uses to handshake receipt of each byte of data. Thus each byte effectively transferred requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA (or the SDAOUT in the 3-wire interface) during the acknowledge clock pulse, so that the SDA line is stable low during the high period of the clock pulse. When the master transmits to the MAX5965A/MAX5965B, the MAX5965A/MAX5965B generate the acknowledge bit. When the MAX5965A/ MAX5965B transmit to the master, the master generates the acknowledge bit.
SDA SDA/ SDAIN SCL SCL S START P STOP . DATA LINE STABLE; CHANGE OF DATA VALID DATA ALLOWED
Figure 6. START and STOP Conditions
Figure 7. Bit Transfer
START CONDITION
CLOCK PULSE FOR ACKNOWLEDGEMENT
SCL
1
2
8
9
SDA BY TRANSMITTER S SDA BY RECEIVER
Figure 8. Acknowledge
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Slave Address The MAX5965A/MAX5965B have a 7-bit long slave address (Figure 9). The bit following the 7-bit slave address (bit eight) is the R/W bit, which is low for a write command and high for a read command. 010 always represents the first 3 bits (MSBs) of the MAX5965A/MAX5965B slave address. Slave address bits A3, A2, A1, and A0 represent the states of the MAX5965A/MAX5965B's A3, A2, A1, and A0 inputs, allowing up to sixteen MAX5965A/MAX5965B devices to share the bus. The states of the A3, A2, A1, and A0 latch in upon the reset of the MAX5965A/MAX5965B into register R11h. The MAX5965A/MAX5965B monitor the bus continuously, waiting for a START condition followed by the MAX5965A/MAX5965B's slave address. When a MAX5965A/MAX5965B recognizes its slave address, the MAX5965A/MAX5965B acknowledge and are then ready for continued communication. Global Addressing and Alert Response Protocol The global address call is used in writing mode to write the same register to multiple devices (address 0x60). In read mode (address 0x61), the global address call is used as the alert response address. When responding to a global call, the MAX5965A/MAX5965B put their own address out on the data line whenever the interrupt is active. Every other device connected to the SDAOUT line that has an active interrupt also does this. After every bit transmitted, the MAX5965A/MAX5965B check that the data line effectively corresponds to the data it
is delivering. If it is not, it then backs off and frees the data line. This litigation protocol always allows the part with the lowest address to complete the transmission. The microcontroller can then respond to the interrupt and take proper actions. The MAX5965A/MAX5965B do not reset their own interrupt at the end of the alert response protocol. The microcontroller has to do it by clearing the event register through their CoR adresses or activating the CLR_INT pushbutton.
MAX5965A/MAX5965B
Message Format for Writing to the MAX5965A/MAX5965B A write to the MAX5965A/MAX5965B comprises of the MAX5965A/MAX5965B's slave address transmission with the R/W bit set to 0, followed by at least 1 byte of information. The first byte of information is the command byte (Figure 10). The command byte determines which register of the MAX5965A/MAX5965B is written to by the next byte, if received. If the MAX5965A/ MAX5965B detect a STOP condition after receiving the command byte, the MAX5965A/MAX5965B take no further action beyond storing the command byte. Any bytes received after the command byte are data bytes. The first data byte goes into the internal register of the MAX5965A/MAX5965B selected by the command byte. If the MAX5965A/MAX5965B transmit multiple data bytes before the MAX5965A/MAX5965B detect a STOP condition, these bytes store in subsequent MAX5965A/ MAX5965B internal registers because the control byte address autoincrements.
MSB SDAIN/SDA 0 1 0 A3 A2 A1
LSB A0 R/W ACK
SCL
Figure 9. Slave Address
CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION ACKNOWLEDGE FROM THE MAX5965A/MAX5965B S SLAVE ADDRESS R/W 0 A
D15
D14
D13
D12
D11
D10
D9
D8
CONTROL BYTE ACKNOWLEDGE FROM THE MAX5965A/MAX5965B
A
P
Figure 10. Control Byte Received
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Message Format for Reading The MAX5965A/MAX5965B read using the MAX5965A/ MAX5965B's internally stored command byte as an address pointer, the same way the stored command byte is used as an address pointer for a write. The pointer autoincrements after reading each data byte using the same rules as for a write. Thus, a read is initiated by first configuring the MAX5965A/MAX5965B's command byte by performing a write (Figure 11). The master now reads `n' consecutive bytes from the MAX5965A/MAX5965B, with the first data byte read from the register addressed by the initialized command byte (Figure 12). When performing read-after-write verification, remember to reset the command byte's address because the stored control byte address autoincrements after the write. Operation with Multiple Masters When the MAX5965A/MAX5965B operate on a 2-wire interface with multiple masters, a master reading the MAX5965A/MAX5965B should use repeated starts between the write which sets the MAX5965A/ MAX5965B's address pointer, and the read(s) that take the data from the location(s). It is possible for master 2 to take over the bus after master 1 has set up the
MAX5965A/MAX5965B's address pointer but before master 1 has read the data. If master 2 subsequently resets the MAX5965A/MAX5965B's address pointer then master 1's read may be from an unexpected location.
Command Address Autoincrementing Address autoincrementing allows the MAX5965A/ MAX5965B to be configured with fewer transmissions by minimizing the number of times the command address needs to be sent. The command address stored in the MAX5965A/MAX5965B generally increments after each data byte is written or read (Table 5). The MAX5965A/MAX5965B are designed to prevent overwrites on unavailable register addresses and unintentional wrap-around of addresses.
Table 5. Autoincrement Rules
COMMAND BYTE ADDRESS RANGE 0x00 to 0x26 0x26 AUTOINCREMENT BEHAVIOR Command address autoincrements after byte read or written Command address remains at 0x26 after byte written or read
ACKNOWLEDGE FROM THE MAX5965A/MAX5965B HOW CONTROL BYTE AND DATA BYTE MAP INTO THE REGISTER ACKNOWLEDGE FROM THE MAX5965A/MAX5965B S SLAVE ADDRESS R/W 0 A D15 D14 D13 D12 D11 D10 D9 D8
ACKNOWLEDGE FROM THE MAX5965A/MAX5965B D7 D6 D5 D4 D3 D2 D1 D0
CONTROL BYTE
A
DATA BYTE 1 BYTE
A
P
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 11. Control and Single Data Byte Received
ACKNOWLEDGE FROM THE MAX5965A/MAX5965B HOW CONTROL BYTE AND DATA BYTE MAP INTO THE REGISTER ACKNOWLEDGE FROM THE MAX5965A/MAX5965B S SLAVE ADDRESS R/W 0 A D15 D14 D13 D12 D11 D10 D9 D8
ACKNOWLEDGE FROM THE MAX5965A/MAX5965B D7 D6 D5 D4 D3 D2 D1 D0
CONTROL BYTE
A
DATA BYTE n BYTES
A
P
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 12. `n' Data Bytes Received
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Register Map and Description
The interrupt register (Table 6) summarizes the event register status and is used to send an interrupt signal (INT goes low) to the controller. Writing a 1 to R1Ah[7] clears all interrupt and events registers. A reset sets R00h to 00h. INT_EN (R17h[7]) is a global interrupt mask (Table 7). The MASK_ bits activate the corresponding interrupt bits in register R00h. Writing a 0 to INT_EN (R17h[7]) disables the INT output. A reset sets R01h to AAA00A00b where A is the state of the AUTO input prior to the reset.
MAX5965A/MAX5965B
Table 6. Interrupt Register
ADDRESS = 00h SYMBOL SUP_FLT TSTR_FLT IMAX_FLT CL_END DET_END LD_DISC PG_INT PE_INT BIT 7 6 5 4 3 2 1 0 R/W R R R R R R R R DESCRIPTION Interrupt signal for supply faults. SUP_FLT is the logic OR of all the bits [7:0] in register R0Ah/R0Bh (Table 12). Interrupt signal for startup failures. TSTR_FLT is the logic OR of bits [7:0] in register R08h/R09h (Table 11). Interrupt signal for current-limit violations. IMAX_FLT is the logic OR of bits [3:0] in register R06h/R07h (Table 10). Interrupt signal for completion of classification. CL_END is the logic OR of bits [7:4] in register R04h/R05h (Table 9). Interrupt signal for completion of detection. DET_END is the logic OR of bits [3:0] in register R04h/R05h (Table 9). Interrupt signal for load disconnection. LD_DISC is the logic OR of bits [7:4] in register R06h/R07h (Table 10). Interrupt signal for PGOOD status change. PG_INT is the logic OR of bits [7:4] in register R02h/R03h (Table 8). Interrupt signal for power-enable status change. PEN_INT is the logic OR of bits [3:0] in register R02h/R03h (Table 8).
Table 7. Interrupt Mask Register
ADDRESS = 01h SYMBOL MASK7 MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION Interrupt mask bit 7. A logic-high enables the SUP_FLT interrupts. A logic-low disables the SUP_FLT interrupts. Interrupt mask bit 6. A logic-high enables the TSTR_FLT interrupts. A logic-low disables the TSTR_FLT interrupts. Interrupt mask bit 5. A logic-high enables the IMAX_FLT interrupts. A logic-low disables the IMAX_FLT interrupts. Interrupt mask bit 4. A logic-high enables the CL_END interrupts. A logic-low disables the CL_END interrupts. Interrupt mask bit 3. A logic-high enables the DET_END interrupts. A logic-low disables the DET_END interrupts. Interrupt mask bit 2. A logic-high enables the LD_DISC interrupts. A logic-low disables the LD_DISC interrupts. Interrupt mask bit 1. A logic-high enables the PG_INT interrupts. A logic-low disables the PG_INT interrupts. Interrupt mask bit 0. A logic-high enables the PEN_INT interrupts. A logic-low disables the PEN_INT interrupts.
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
The power event register (Table 8) records changes in the power status of the four ports. Any change in PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change in the PWR_EN_ (R10h[3:0]) sets PWEN_CHG_ to 1. PG_CHG_ and PWEN_CHG_ trigger on the edges of PGOOD_ and PWR_EN_ and do not depend on the actual level of the bits. The power event register has two addresses. When read through the R02h address, the content of the register is left unchanged. When read through the CoR R03h address, the register content is cleared. A reset sets R02h/R03h = 00h.
Table 8. Power Event Register
ADDRESS SYMBOL PG_CHG4 PG_CHG3 PG_CHG2 PG_CHG1 PWEN_CHG4 PWEN_CHG3 PWEN_CHG2 PWEN_CHG1 BIT 7 6 5 4 3 2 1 0 02h R/W R R R R R R R R 03h R/W CoR CoR CoR CoR CoR CoR CoR CoR PGOOD change event for port 4 PGOOD change event for port 3 PGOOD change event for port 2 PGOOD change event for port 1 Power enable change event for port 4 Power enable change event for port 3 Power enable change event for port 2 Power enable change event for port 1 DESCRIPTION
DET_END_/CL_END_ is set high whenever detection/ classification is completed on the corresponding port. A 1 in any of the CL_END_ bits forces R00h[4] to 1. A 1 in any of the DET_END_ bits forces R00h[3] to 1. As with any of the other events register, the detect event register
has two addresses. When read through the R04h address, the content of the register is left unchanged. When read through the CoR R05h address, the register content is cleared. A reset sets R04h/R05h = 00h.
Table 9. Detect Event Register
ADDRESS SYMBOL CL_END4 CL_END3 CL_END2 CL_END1 DET_END4 DET_END3 DET_END2 DET_END1 BIT 7 6 5 4 3 2 1 0 04h R/W R R R R R R R R 05h R/W CoR CoR CoR CoR CoR CoR CoR CoR Classification completed on port 4 Classification completed on port 3 Classification completed on port 2 Classification completed on port 1 Detection completed on port 4 Detection completed on port 3 Detection completed on port 2 Detection completed on port 1 DESCRIPTION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
LD_DISC_ is set high whenever the corresponding port shuts down due to detection of load removal. IMAX_FLT_ is set high when the port shuts down due to an extended overcurrent event after a successful startup. A 1 in any of the LD_DISC_ bits forces R00h[2] to 1. A 1 in any of the IMAX_FLT_ bits forces R00h[5] to 1. As with any of the other events register, the fault event register has two addresses. When read through the R06h address, the content of the register is left unchanged. When read through the CoR R07h address, the register content is cleared. A reset sets R06h/R07h = 00h.
MAX5965A/MAX5965B
Table 10. Fault Event Register
ADDRESS SYMBOL LD_DISC4 LD_DISC3 LD_DISC2 LD_DISC1 IMAX_FLT4 IMAX_FLT3 IMAX_FLT2 IMAX_FLT1 BIT 7 6 5 4 3 2 1 0 06h R/W R R R R R R R R 07h R/W CoR CoR CoR CoR CoR CoR CoR CoR Disconnect on port 4 Disconnect on port 3 Disconnect on port 2 Disconnect on port 1 Overcurrent on port 4 Overcurrent on port 3 Overcurrent on port 2 Overcurrent on port 1 DESCRIPTION
If the port remains in current limit or the PGOOD condition is not met at the end of the startup period, the port shuts down and the corresponding STRT_FLT_ is set to 1. A 1 in any of the STRT_FLT_ bits forces R00h[6] to 1. IVC_ is set to 1 whenever the port current exceeds the maximum allowed limit for the class (determined during the classification process). A 1 in any of IVC_ forces R00h[6] to 1. When the CL_DISC (R17h[2]) is set to 1,
the port also limits the load current according to its class as specified in the Electrical Characteristics table. As with any of the other events register, the startup event register has two addresses. When read through the R08h address, the content of the register is left unchanged. When read through the CoR R09h address, the register content is cleared. A reset sets R08h/R09h = 00h.
Table 11. Startup Event Register
ADDRESS SYMBOL IVC4 IVC3 IVC2 IVC1 STRT_FLT4 STRT_FLT3 STRT_FLT2 STRT_FLT1 BIT 7 6 5 4 3 2 1 0 08h R/W R R R R R R R R 09h R/W CoR CoR CoR CoR CoR CoR CoR CoR Class overcurrent flag for port 4 Class overcurrent flag for port 3 Class overcurrent flag for port 2 Class overcurrent flag for port 1 Startup failed on port 4 Startup failed on port 3 Startup failed on port 2 Startup failed on port 1 DESCRIPTION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
The MAX5965A/MAX5965B continuously monitor the power supplies and set the appropriate bits in the supply event register (Table 12). VDD_OV/VEE_OV is set to 1 whenever VDD/VEE exceeds its overvoltage threshold. V DD_UV /V EE_UV is set to 1 whenever V DD /V EE falls below its undervoltage threshold. OSC_FAIL is set to 1 whenever the amplitude of the oscillator signal at the OSC_ input falls below a level that might compromise the AC disconnect detection function. OSC_FAIL generates an interrupt only if at least one of the ACD_EN (R13h[7:4]) bits is set high. A thermal shutdown circuit monitors the temperature of the die and resets the MAX5965A/MAX5965B if the temperature exceeds +150C. TSD is set to 1 after the MAX5965A/MAX5965B return to normal operation. TSD is also set to 1 after every UVLO reset. When VDD and/or |VEE| is below its UVLO threshold, the MAX5965A/MAX5965B are in reset mode and securely holds all ports off. When VDD and |VEE| rise to above their respective UVLO thresholds, the device comes out of reset as soon as the last supply crosses the UVLO threshold. The last supply corresponding UV and UVLO bits in the supply event register is set to 1. A 1 in any supply event register's bits forces R00h[7] to 1. As with any of the other events register, the supply event register has two addresses. When read through the R0Ah address, the content of the register is left unchanged. When read through the CoR R0Bh address, the register content is cleared. A reset sets R0Ah/R0Bh to 00100001b if VDD comes up after VEE or to 00010100b if VEE comes up after VDD.
Table 12. Supply Event Register
ADDRESS SYMBOL TSD VDD_OV VDD_UV VEE_UVLO VEE_OV VEE_UV OSC_FAIL VDD_UVLO BIT 7 6 5 4 3 2 1 0 0Ah R/W R R R R R R R R 0Bh R/W CoR CoR CoR CoR CoR CoR CoR CoR Overtemperature shutdown VDD overvoltage condition VDD undervoltage condition VEE undervoltage lockout condition VEE overvoltage condition VEE undervoltage condition Oscillator amplitude is below limit VDD undervoltage lockout condition DESCRIPTION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
The port status register (Table 13a) records the results of the detection and classification at the end of each phase in three encoding bits each. R0Ch contains the detection and classification status of port 1. R0Dh corresponds to port 2, R0Eh corresponds to port 3, and R0Fh corresponds to port 4. Tables 13b and 13c show the detection/classification result decoding charts, respectively. For CLC_EN = 0, the detection result is shown in Table 13b. When CLC_EN is set high, the MAX5965A/MAX5965B allow valid detection of high capacitive load of up to 150F. When 2-event classification is not enabled (ENx_CL6 = 0), the classification status is reported in Table 13c. When 2-event classification is enabled (ENx_CL6 = 1), the CLASS_[2:0] bits are set to 000 and the classification result is reported in locations R2Ch-R2Fh. As a protection, when POFF_CL (R17h[3], Table 21) is set to 1, the MAX5965A/MAX5965B prohibit turning on power to the port that returns a status 111 after classification. A reset sets 0Ch, 0Dh, 0Eh, and 0Fh = 00h.
MAX5965A/MAX5965B
Table 13a. Port Status Registers
ADDRESS = 0Ch, 0Dh, 0Eh, 0Fh SYMBOL Reserved CLASS_ Reserved DET_ST_ BIT 7 6 5 4 3 2 1 0 R/W R R R R R R R R Reserved CLASS_[2] CLASS_[1] CLASS_[0] Reserved DET_[2] DET_[1] DET_[0] DESCRIPTION
Table 13b. Detection Result Decoding Chart
DET_ST_[2:0] (ADDRESS = 0Ch, 0Dh, 0Eh, 0Fh) 000 001 010 011 100 101 110 111 DETECTED None DCP HIGH CAP RLOW DET_OK RHIGH OPEN0 DCN Detection status unknown Positive DC supply connected at the port (AGND - VOUT_ < 1V) High capacitance at the port (> 8.5F) Low resistance at the port, RPD < 15k Detection pass, 15k < RPD < 33k High resistance at the port, RPD > 33k Open port (I < 10A) Negative DC supply connected to the port (VOUT - VEE < 2V) DESCRIPTION
Table 13c. Classification Result Decoding Chart
CLASS_[2:0] (ADDRESS = 0Ch, 0Dh, 0Eh, 0Fh) 000 001 010 011 100 101 110 111 CLASS RESULT Unknown 1 2 3 4 5 0 Current limit (> ICILIM)
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
PGOOD_ is set to 1 (Table 14) at the end of the powerup startup period if the power-good condition is met (0 < (VOUT - VEE) < PGTH). The power-good condition must remain valid for more than t PGOOD to assert PGOOD_. PGOOD_ is reset to 0 whenever the output falls out of the power-good condition. A fault condition immediately forces PGOOD_ low. PWR_EN_ is set to 1 when the port power is turned on. PWR_EN resets to 0 as soon as the port turns off. Any transition of PGOOD_ and PWR_EN_ bits set the corresponding bit in the power event registers R02h/R03h (Table 8). A reset sets R10h = 00h.
Table 14. Power Status Register
ADDRESS = 10h SYMBOL PGOOD4 PGOOD3 PGOOD2 PGOOD1 PWR_EN4 PWR_EN3 PWR_EN2 PWR_EN1 BIT 7 6 5 4 3 2 1 0 R/W R R R R R R R R Power-good condition on port 4 Power-good condition on port 3 Power-good condition on port 2 Power-good condition on port 1 Power is enabled on port 4 Power is enabled on port 3 Power is enabled on port 2 Power is enabled on port 1 DESCRIPTION
A3, A2, A1, A0 (Table 15) represent the 4 LSBs of the MAX5965A/MAX5965B address (Table 4). During a reset, the device latches into R11h. These 4 bits
address from the corresponding inputs as well as the state of the MIDSPAN and AUTO inputs. Changes to those inputs during normal operation are ignored.
Table 15. Address Input Status Register
ADDRESS = 11h SYMBOL Reserved Reserved A3 A2 A1 A0 MIDSPAN AUTO BIT 7 6 5 4 3 2 1 0 R/W R R R R R R R R Reserved Reserved Device address, A3 pin latched-in status Device address, A2 pin latched-in status Device address, A1 pin latched-in status Device address, A0 pin latched-in status MIDSPAN input's latched-in status AUTO input's latched-in status DESCRIPTION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
The MAX5965A/MAX5965B use 2 bits for each port to set the mode of operation. Set the modes according to Table 16a and 16b. A reset sets R12h = AAAAAAAA where A represents the latched-in state of the AUTO input prior to the reset. Use software to change the mode of operation. Software resets of ports (RESET_P_ bit, Table 23) do not affect the mode register.
MAX5965A/MAX5965B
Table 16a. Operating Mode Register
ADDRESS = 12h SYMBOL P4_M1 P4_M0 P3_M1 P3_M0 P2_M1 P2_M0 P1_M1 P1_M0 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W MODE[1] for port 4 MODE[0] for port 4 MODE[1] for port 3 MODE[0] for port 3 MODE[1] for port 2 MODE[0] for port 2 MODE[1] for port 1 MODE[0] for port 1 DESCRIPTION
Table 16b. Operating Mode Status
MODE 00 01 10 11 Shutdown Manual Semi-auto Auto DESCRIPTION
Setting DCD_EN_ to 1 enables the DC load disconnect detection feature (Table 17). Setting ACD_EN_ to 1 enables the AC load disconnect feature. If enabled, the load disconnect detection starts during power mode
and after startup when the corresponding PGOOD_ bit in register R10h (Table 14) goes high. A reset sets R13h = 0000AAAA where A represents the latched-in state of the AUTO input prior to the reset.
Table 17. Load Disconnect Detection Enable Register
ADDRESS = 13h SYMBOL ACD_EN4 ACD_EN3 ACD_EN2 ACD_EN1 DCD_EN4 DCD_EN3 DCD_EN2 DCD_EN1 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION Enable AC disconnect detection on port 4 Enable AC disconnect detection on port 3 Enable AC disconnect detection on port 2 Enable AC disconnect detection on port 1 Enable DC disconnect detection on port 4 Enable DC disconnect detection on port 3 Enable DC disconnect detection on port 2 Enable DC disconnect detection on port 1
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Setting DET_EN_/CLASS_EN_ to 1 (Table 18) enables load detection/classification, respectively. Detection always has priority over classification. To perform classification without detection, set the DET_EN_ bit low and CLASS_EN_ bit high. In manual mode, R14h works like a pushbutton. Set the bits high to begin the corresponding routine. The bit clears after the routine finishes. When entering auto mode, R14h defaults to FFh. When entering semi or manual modes, R14h defaults to 00h. A reset or power-up sets R14h = AAAAAAAAb where A represents the latched-in state of the AUTO input prior to the reset.
Table 18. Detection and Classification Enable Register
ADDRESS = 14h SYMBOL CLASS_EN4 CLASS_EN3 CLASS_EN2 CLASS_EN1 DET_EN4 DET_EN3 DET_EN2 DET_EN1 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Enable classification on port 4 Enable classification on port 3 Enable classification on port 2 Enable classification on port 1 Enable detection on port 4 Enable detection on port 3 Enable detection on port 2 Enable detection on port 1 DESCRIPTION
EN_HP_CL, EN_HP_ALL together with CL_DISC (R17h[2]) and ENx_CL6 (R1Ch[7:4]) are used to program the high-power mode. See Table 3 for details. Setting BCKOFF_ to 1 (Table 19) enables cadence timing on each port where the port backs off and waits 2.2s after each failed load discovery detection. The
IEEE 802.3af standard requires a PSE that delivers power through the spare pairs (midspan PSE) to have cadence timing. A reset or power-up sets R15h = 0000XXXXb where `X' is the logic AND of the MIDSPAN and AUTO inputs.
Table 19. Backoff and High-Power Enable Register
ADDRESS = 15h SYMBOL EN_HP_ALL EN_HP_CL6 EN_HP_CL5 EN_HP_CL4 BCKOFF4 BCKOFF3 BCKOFF2 BCKOFF1 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W High-power detection enabled Class 6 PD high-power enabled Class 5 PD high-power enabled Class 4 PD high-power enabled Enable cadence timing on port 4 Enable cadence timing on port 3 Enable cadence timing on port 2 Enable cadence timing on port 1 DESCRIPTION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
TSTART[1,0] (Table 20a) programs the startup timers. Startup time is the time the port is allowed to be in current limit during startup. TFAULT[1,0] programs the fault time. Fault time is the time allowed for the port to be in current limit during normal operation. RSTR[1,0] programs the discharge rate of the TFAULT_ counter and effectively sets the time the port remains off after an overcurrent fault. TDISC[1,0] programs the load disconnect detection time. The device turns off power to the port if it fails to provide a minimum power maintenance signal for longer than the load disconnect detection time (TDISC). Set the bits in R16h to scale the tSTART, tFAULT, and tDISC to a multiple of their nominal value specified in the Electrical Characteristics table. When the MAX5965A/MAX5965B shut down a port due to an extended overcurrent condition (either during startup or normal operation), if RSTR_EN is set high, the part does not allow the port to power back on before the restart timer (Table 20b) returns to zero. This effectively sets a minimum duty cycle that protects the external MOSFET from overheating during prolonged output overcurrent conditions. A reset sets R16h = 00h.
MAX5965A/MAX5965B
Table 20a. Timing Configuration Register
ADDRESS = 16h SYMBOL RSTR[1] RSTR[0] TSTART[1] TSTART[0] TFAULT[1] TFAULT[0] TDISC[1] TDISC[0] BIT 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Restart timer programming bit 1 Restart timer programming bit 0 Startup timer programming bit 1 Startup timer programming bit 0 Overcurrent timer programming bit 1 Overcurrent timer programming bit 0 Load disconnect timer programming bit 1 Load disconnect timer programming bit 0 DESCRIPTION
Table 20b. Startup, Fault, and Load Disconnect Timer Values for Timing Register
BIT [1:0] (ADDRESS = 16h) 00 01 10 11 RSTR 16 x tFAULT 32 x tFAULT 64 x tFAULT 0 x tFAULT tDISC tDISC nominal (350ms, typ) 1/4 x tDISC nominal 1/2 x tDISC nominal 2 x tDISC nominal tSTART tSTART nominal (60ms, typ) 1/2 x tSTART nominal 2 x tSTART nominal 4 x tSTART nominal tFAULT tFAULT nominal (60ms, typ) 1/2 x tFAULT nominal 2 x tFAULT nominal 4 x tFAULT nominal
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Setting CL_DISC to 1 (Table 21) enables port over class current protection, where the MAX5965A/MAX5965B scales down the overcurrent limit (VFLT_LIM) according to the port classification status. This feature provides protection to the system against PDs that violate their maximum class current allowance. The MAX5965 is programmed to switch to a high-power configuration and HP_TIME is low, the higher current setting is enabled only after a successful startup so that the PD powers up as a normal 15W device. If HP_TIME is set together with EN_HP_ALL, the higher current setting will be active before startup. For Classes 4, 5, and 6, the corresponding enable bit in register R15h must be set together with EN_HP_ALL. In any other cases, the current level defaults to Class 0. CL_DISC, together with EN_HP_CL_ (R15h[6:4]), EN_HP_ALL (R15h[7]), and ENx_CL6 (R1Ch[7:4]) are used to program the high-power mode. See Table 3 for details. Setting OUT_ISO high (Table 21), forces DET_ to a high-impedance state. A reset sets R17h = 0xC0.
Table 21. Miscellaneous Configurations 1 Register
ADDRESS = 17h SYMBOL INT_EN RSTR_EN Reserved Reserved POFF_CL CL_DISC BIT 7 6 5 4 3 2 R/W R/W R/W -- -- R R/W A logic-high enables INT functionality A logic-high enables the autorestart protection time off (as set by the RSTR[1:0] bits) Reserved Reserved A logic-high prevents power-up after a classification failure (I > 50mA, valid only in AUTO mode) A logic-high enables reduced current-limit voltage threshold (VFLT_LIM) according to port classification result DESCRIPTION
Power-enable pushbutton for semi and manual modes is found in Table 22. Setting PWR_ON_ to 1 turns on power to the corresponding port. Setting PWR_OFF_ to 1 turns off power to the port. PWR_ON_ is ignored when the port is already powered and during shutdown. PWR_OFF_ is ignored when the port is already off and
during shutdown. After execution, the bits reset to 0. During detection or classification, if PWR_ON_ goes high, the MAX5965A/MAX5965B gracefully terminate the current operation and turn on power to the port. The MAX5965A/MAX5965B ignore the PWR_ON_ in auto mode. A reset sets R19h = 00h.
Table 22. Power-Enable Pushbuttons Register
ADDRESS = 19h SYMBOL PWR_OFF4 PWR_OFF3 PWR_OFF2 PWR_OFF1 PWR_ON4 PWR_ON3 PWR_ON2 PWR_ON1 BIT 7 6 5 4 3 2 1 0 R/W W W W W W W W W A logic-high powers off port 4 A logic-high powers off port 3 A logic-high powers off port 2 A logic-high powers off port 1 A logic-high powers on port 4 A logic-high powers on port 3 A logic-high powers on port 2 A logic-high powers on port 1 DESCRIPTION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Writing a 1 to CLR_INT (Table 23) clears all the event registers and the corresponding interrupt bits in register R00h. Writing a 1 to RESET_P_ turns off power to the corresponding port and resets only the status and event registers of that port. After execution, the bits reset to 0. Writing a 1 to RESET_IC causes a global software reset, after which the register map is set back to its reset state. A reset sets R1Ah = 00h.
MAX5965A/MAX5965B
Table 23. Global Pushbuttons Register
ADDRESS = 1Ah SYMBOL CLR_INT Reserved Reserved RESET_IC RESET_P4 RESET_P3 RESET_P2 RESET_P1 BIT 7 6 5 4 3 2 1 0 R/W W -- -- W W W W W A logic-high clears all interrupts Reserved Reserved A logic-high resets the MAX5965A/MAX5965B A logic-high resets port 4 A logic-high resets port 3 A logic-high resets port 2 A logic-high resets port 1 DESCRIPTION
The ID register (Table 24) keeps track of the device ID number and revision. The MAX5965A/MAX5965B's
ID_CODE[4:0] = 11000b. Contact the factory for REV[2:0] value.
Table 24. ID Register
ADDRESS = 1Bh SYMBOL BIT 7 6 ID_CODE 5 4 3 2 REV 1 0 R/W R R R R R R R R ID_CODE[4] ID_CODE[3] ID_CODE[2] ID_CODE[1] ID_CODE[0] REV[2] REV[1] REV[0] DESCRIPTION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Enable 2-event classification for a port by setting the corresponding ENx_CL6 bit (Table 25). When the bit is enabled, the classification cycle will be repeated three times at 21.3ms intervals. The device keeps the output voltage around -9V between each cycle. The repetition of the classification cycles enables discovering of class 6 PDs. The ENx_CL6 bit is active only in auto- or semi-mode. Note: Performing three consecutive classifications in manual mode is not the same as performing 2-event classification in semi or auto mode. Enable the SMODE function (Table 25) by setting EN_WHDOG (R1Fh[7]) to 1. The SMODE_ bit goes high when the watchdog counter reaches zero and the port(s) switch over to hardware-controlled mode. SMODE_ also goes high each and every time the software tries to power on a port, but is denied since the port is in hardware mode. A reset sets R1Ch = 00h.
Table 25. SMODE and 2-Event Enable Register
ADDRESS = 1Ch SYMBOL EN4_CL6 EN3_CL6 EN2_CL6 EN1_CL6 SMODE4 SMODE3 SMODE2 SMODE1 BIT 7 6 5 4 3 2 1 0 CoR or R/W R/W R/W R/W R/W CoR CoR CoR CoR DESCRIPTION Port 4 2-event classification enabled Port 3 2-event classification enabled Port 2 2-event classification enabled Port 1 2-event classification enabled Port 4 hardware control flag Port 3 hardware control flag Port 2 hardware control flag Port 1 hardware control flag
Set EN_WHDOG (R1Fh[7]) to 1 to enable the watchdog function. When activated, the watchdog timer counter, WDTIME[7:0], continuously decrements toward zero once every 164ms. Once the counter reaches zero (also called watchdog expiry), the MAX5965A/ MAX5965B enter hardware-controlled mode and each port shifts to a mode set by the HWMODE_ bit in register R1Fh (Table 27). Use software to set WDTIME (Table 26) and continuously set this register to some nonzero value before the register reaches zero to pre-
vent a watchdog expiry. In this way, the software gracefully manages the power to ports upon a system crash or switchover. While in hardware-controlled mode, the MAX5965A/ MAX5965B ignore all requests to turn the power on and the flag SMODE_ indicates that the hardware has taken control of the MAX5965A/MAX5965B operation. In addition, the software is not allowed to change the mode of operation in hardware-controlled mode. A reset sets R1Eh = 00h.
Table 26. Watchdog Register
ADDRESS = 1Eh SYMBOL BIT 7 6 5 WDTIME 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W WDTIME[7] WDTIME[6] WDTIME[5] WDTIME[4] WDTIME[3] WDTIME[2] WDTIME[1] WDTIME[0] DESCRIPTION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Setting EN_WHDOG (Table 27) high activates the watchdog counter. When the counter reaches zero, the port switches to the hardware-controlled mode determined by the corresponding HWMODE_ bit. A low in HWMODE_ switches the port into shutdown by setting the bits in register R12h to 00. A high in HWMODE_ switches the port into auto mode by setting the bits in register R12h to 11. If WD_INT_EN is set, an interrupt is sent if any of the SMODE bits are set. A reset sets R1Fh = 00h.
MAX5965A/MAX5965B
Table 27. Switch Mode Register
ADDRESS = 1Fh SYMBOL EN_WHDOG WD_INT_EN Reserved Reserved HWMODE4 HWMODE3 HWMODE2 HWMODE1 BIT 7 6 5 4 3 2 1 0 R/W R/W R/W -- -- R/W R/W R/W R/W Enables interrupt on SMODE_ bits Reserved Reserved Port 4 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer expires Port 3 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer expires Port 2 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer expires Port 1 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer expires DESCRIPTION A logic-high enables the watchdog function
The CLC_EN enables the large capacitor detection feature. When CLC_EN is set the device can recognize a capacitor load up to 150F. If the CLC_EN is reset, the MAX5965A/MAX5965B perform normal detection. AC_TH allows programming of the threshold of the AC disconnect comparator. The threshold is defined as a current since the comparators verify that the peak of the current pulses sensed at the DET_ input exceed a preset threshold. The current threshold is defined as follows:
IAC_TH = 226.68A + 28.33 x NAC_TH where NAC_TH is the decimal value of AC_TH. When set low, DET_BY inhibits port power-on if the discovery detection was bypassed in auto mode. When set high, DET_BY allows the device to turn on power to a non-IEEE 802.3af load without doing detection. If OSCF_RS is set high, the OSC_FAIL bit is ignored. A reset or power-up sets R23h = 04h. Default IAC_TH is 340A.
Table 28. Program Register
ADDRESS = 23h SYMBOL Reserved Reserved CLC_EN DET_BY OSCF_RS AC_TH BIT 7 6 5 4 3 2 1 0 R/W -- -- R/W R/W R/W R/W R/W R/W Reserved Reserved Large capacitor detection enable Enables skipping detection in AUTO mode OSC_FAIL reset bit AC_TH[2] AC_TH[1] AC_TH[0] DESCRIPTION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
HP[2:0] programs the default power setting that is written upon the discovery of a class 4, 5, or 6 PD. A reset or power-up sets R24h = 00h.
Table 29. High-Power Mode Register
ADDRESS = 24h SYMBOL Reserved HP BIT 7 6 5 4 3 Reserved 2 1 0 R/W -- R/W R/W R/W -- -- -- -- Reserved HP[2] HP[1] HP[0] Reserved Reserved Reserved Reserved DESCRIPTION
Table 30. Reserved Register (25h)
ADDRESS = 25h SYMBOL BIT 7 6 5 Reserved 4 3 2 1 0 R/W -- -- -- -- -- -- -- -- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DESCRIPTION
Table 31. Reserved Register (26h)
ADDRESS = 26h SYMBOL BIT 7 6 5 Reserved 4 3 2 1 0 R/W -- -- -- -- -- -- -- -- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DESCRIPTION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
The IVEE bits enable the current-limit scaling (Table 32). This feature is used to reduce the current limit for systems running at higher voltage to maintain the desired output power. Table 33 sets the current-limit scaling register. A reset or power-up sets R29h = 00h.
MAX5965A/MAX5965B
Table 32. Miscellaneous Configurations 2
ADDRESS = 29h SYMBOL BIT 7 6 Reserved 5 4 3 2 IVEE 1 0 R/W -- -- -- -- -- -- R/W R/W DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved IVEE[1] IVEE[0]
Table 33. Current-Limit Scaling Register
IVEE[1:0] (ADDRESS = 29h) 00 01 10 11 CURRENT LIMIT (%) Default -5 -10 -15
The three ICUT_ bits (Tables 34a and 34b) allow programming of the current-limit and overcurrent thresholds in excess of the IEEE 802.3af standard limit. The MAX5965A/MAX5965B can automatically set the ICUT register or can be manually written to by the software (see Table 3).
Class 1 and 2 limits can also be programmed by software independently from the classification status. See Table 3. A reset or power-up sets R2Ah = R2Bh = 00h.
Table 34a. ICUT Registers 1 and 2
ADDRESS = 2Ah SYMBOL Reserved ICUT2 Reserved ICUT1 BIT 7 6 5 4 3 2 1 0 R/W -- R/W R/W R/W -- R/W R/W R/W Reserved ICUT2[2] ICUT2[1] ICUT2[0] Reserved ICUT1[2] ICUT1[1] ICUT1[0] DESCRIPTION
Table 34b. ICUT Registers 3 and 4
ADDRESS = 2Bh SYMBOL Reserved ICUT4 Reserved ICUT3 BIT 7 6 5 4 3 2 1 0 R/W -- R/W R/W R/W -- R/W R/W R/W Reserved ICUT4[2] ICUT4[1] ICUT4[0] Reserved ICUT3[2] ICUT3[1] ICUT3[0] DESCRIPTION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Table 34c. ICUT Register Bit Values for Current-Limit Threshold
ICUT_[2:0] (ADDRESS = 2Ah, 2Bh) 000 001 010 011 100 101 110 111 SCALE FACTOR 1x 1.5x 1.75x 2x 2.25x 2.5x 0.3x 0.53x TYPICAL CURRENT-LIMIT THRESHOLD (mA) 375 563 656 750 844 938 Class 1 Class 2
Table 35a. Classification Status Registers
ADDRESS = 2Ch, 2Dh, 2Eh, 2Fh SYMBOL Reserved BIT 7 6 R/W -- -- Reserved Reserved DESCRIPTION
Table 35b. Class Sequence States
CLASS_[5:0] (ADDRESS = 2Ch, 2Dh, 2Eh, 2Fh) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 CLASS SEQUENCE 000 (Class 0) 001 010 011 100 101 110 111 (Class 1) 002 020 022 200 202 220 222 (Class 2) 003 030 033 300 303 330 ICUT[2:0] 000 000 HP[2:0] 000 000 HP[2:0] 000 110 000 011 000 000 100 000 111 000 010 000 000 010 000 CLASS_[5:0] (ADDRESS = 2Ch, 2Dh, 2Eh, 2Fh) 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 CLASS SEQUENCE 333 (Class 3) 004 040 044 400 404 440 444 (Class 4) 005 050 055 500 505 550 555 (Class 5) Reserved Reserved Reserved Reserved Illegal Illegal ICUT[2:0] 000 000 000 000 000 000 000 HP[2:0] 000 000 000 000 000 000 HP[2:0] 000 000 000 000 000 000
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Table 35b. Class Sequence States (continued)
CLASS_[5:0] (ADDRESS = 2Ch, 2Dh, 2Eh, 2Fh) 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 CLASS SEQUENCE Illegal Illegal Illegal Illegal Illegal Illegal Reserved Reserved Reserved Reserved Reserved ICUT[2:0] 000 000 000 000 000 000 000 000 000 000 000 CLASS_[5:0] (ADDRESS = 2Ch, 2Dh, 2Eh, 2Fh) 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 CLASS SEQUENCE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ICUT[2:0] 000 000 000 000 000 000 000 000 000 000 000
MAX5965A/MAX5965B
When the ENx_CL6 (R1Ch[7:4]) bits are set, 2-event classification is enabled. Classification is repeated three times and the classification results are set according to Table 35b. A Class 6 PD is defined by any sequence of the type [00x, 0x0, 0xx, x00, x0x, xx0] where `x' can be 1, 2, 3, 4, or 5. All sequences made by the same class result define the class itself (for example, 222 defines Class 2). Any other sequence will be considered illegal and coded as 101---. For example, a sequence 232 or 203 will be illegal. The illegal sequences all default to class 0. A reset or power-up sets R2Ch = R2Dh = R2Eh = R2Fh = 00h. The MAX5965A/MAX5965B provide current readout for each port during classification and normal power mode. The current per port information is separated
into 9 bits. They are organized into two consecutive registers for each one of the ports. The information can be quickly retrieved using the autoincrement option of the address pointer. To avoid the LSB register changing while reading the MSB, the information is frozen once the addressing byte points to any of the current readout registers. During power mode, the current value can be calculated as IPORT = NIPD_ x 1.953125mA During classification, the current is ICLASS = NIPD_ x 0.0975mA where NIPD_ is the decimal value of the 9-bit word. The ADC saturates both at full scale and at zero. A reset sets R30h to R37h = 00h.
Table 36. Current Registers
ADDRESS = 30h, 31h, 32h, 33h, 34h, 35h, 36h, 37h SYMBOL BIT 7 6 5 IPD_ 4 3 2 1 0 R/W W W W W W W W W IPD_[8] IPD_[7] IPD_[6] IPD_[5] IPD_[4] IPD_[3] IPD_[2] IPD_[1]/IPD_[0] DESCRIPTION
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Table 37. Register Summary
ADDR REGISTER NAME R/W PORT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE INTERRUPTS 00h 01h EVENTS 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh STATUS 0Ch 0Dh 0Eh 0Fh 10h 11h Port 1 Status Port 2 Status Port 3 Status Port 4 Status Power Status Address Input Status RO RO RO RO RO RO 1 2 3 4 4321 G Reserved Reserved Reserved Reserved PGOOD4 Reserved CLASS1[2] CLASS2[2] CLASS3[2] CLASS4[2] PGOOD3 Reserved CLASS1[1] CLASS2[1] CLASS3[1] CLASS4[1] PGOOD2 A3 CLASS1[0] CLASS2[0] CLASS3[0] CLASS4[0] PGOOD1 A2 Reserved Reserved Reserved Reserved PWR_EN4 A1 DET_ST1[2] DET_ST2[2] DET_ST3[2] DET_ST4[2] PWR_EN3 A0 DET_ST1[1] DET_ST2[1] DET_ST3[1] DET_ST4[1] PWR_EN2 MIDSPAN DET_ST1[0] DET_ST2[0] DET_ST3[0] DET_ST4[0] PWR_EN1 AUTO 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 00A3A2, A1A0MA Power Event Power Event CoR Detect Event Detect Event CoR Fault Event Fault Event CoR Startup Event Startup Event CoR Supply Event Supply Event CoR RO CoR RO CoR RO CoR RO CoR RO CoR 4321 -- 4321 -- 4321 -- 4321 -- 4321 -- PG_CHG4 CL_END4 PG_CHG3 CL_END3 PG_CHG2 CL_END2 PG_CHG1 CL_END1 PWEN_ CHG4 DET_END4 PWEN_ CHG3 DET_END3 PWEN_ CHG2 DET_END2 PWEN_ CHG1 DET_END1 0000,0000 -- 0000,0000 -- 0000,0000 -- 0000,0000 -- 0001,0000* -- Interrupt Interrupt Mask RO R/W G G SUP_FLT MASK7 TSTR_FLT MASK6 IMAX_FLT MASK5 CL_END MASK4 DET_END MASK3 LD_DISC MASK2 PG_INT MASK1 PE_INT MASK0 0000,0000 AAA0,0A00
LD_DISC4
LD_DISC3
LD_DISC2
LD_DISC1
IMAX_FLT4
IMAX_FLT3
IMAX_FLT2
IMAX_FLT1
IVC4
IVC3
IVC2
IVC1
STRT_FLT4
STRT_FLT3
STRT_FLT2
STRT_FLT1
TSD
VDD_OV
VDD_UV
VEE_UVLO
VEE_OV
VEE_UV
OSC_FAIL
VDD_UVLO
CONFIGURATION 12h 13h Operating Mode Load Disconnect Detection Enable Detection and Classification Enable Backoff and HighPower Enable Timing Configuration Miscellaneous Configuration 1 R/W R/W 4321 4321 P4_M1 ACD_EN4 P4_M0 ACD_EN3 P3_M1 ACD_EN2 P3_M0 ACD_EN1 P2_M1 DCD_EN4 P2_M0 DCD_EN3 P1_M1 DCD_EN2 P1_M0 DCD_EN1 AAAA,AAAA 0000,AAAA
14h
R/W
4321
CLASS_EN4
CLASS_EN3
CLASS_EN2
CLASS_EN1
DET_EN4
DET_EN3
DET_EN2
DET_EN1
AAAA,AAAA
15h 16h 17h
R/W R/W R/W
4321 G G
EN_HP_ALL RSTR[1] INT_EN
EN_HP_CL6 RSTR[0] RSTR_EN
EN_HP_CL5 TSTART[1] Reserved
EN_HP_CL4 TSTART[0] Reserved
BCKOFF4 TFAULT[1] POFF_CL
BCKOFF3 TFAULT[0] CL_DISC
BCKOFF2 TDISC[1] OUT_ISO
BCKOFF1 TDISC[0] HP_TIME
0000,XXXX 0000,0000 1100,0000
PUSHBUTTONS 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Reserved Power Enable Global ID SMODE and 2-Event Enable Reserved Watchdog Switch Mode R/W WO WO RO CoR -- R/W R/W G 4321 G G 4321 G G 4321 Reserved PWR_OFF4 CLR_INT ID_CODE[4] EN4_CL6 Reserved WDTIME[7] EN_WHDOG Reserved PWR_OFF3 Reserved ID_CODE[3] EN3_CL6 Reserved WDTIME[6] WD_INT_EN Reserved PWR_OFF2 Reserved ID_CODE[2] EN2_CL6 Reserved WDTIME[5] Reserved Reserved PWR_OFF1 RESET_IC ID_CODE[1] EN1_CL6 Reserved WDTIME[4] Reserved Reserved PWR_ON4 RESET_P4 ID_CODE[0] SMODE4 Reserved WDTIME[3] HWMODE4 Reserved PWR_ON3 RESET_P3 REV[2] SMODE3 Reserved WDTIME[2] HWMODE3 Reserved PWR_ON2 RESET_P2 REV[1] SMODE2 Reserved WDTIME[1] HWMODE2 Reserved PWR_ON1 RESET_P1 REV[0] SMODE1 Reserved WDTIME[0] HWMODE1 -- 0000,0000 0000,0000 1100,0000 0000,0000 -- 0000,0000 0000,0000
GENERAL
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Table 37. Register Summary (continued)
ADDR REGISTER NAME R/W PORT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE MAXIM RESERVED 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh Reserved Reserved Reserved Program High-Power Mode Reserved Reserved Reserved Reserved Miscellaneous Configuration 2 -- -- -- R/W R/W -- -- -- -- R/W G G G 4321 G G G G G 1234 21 43 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved HP[2] Reserved Reserved Reserved Reserved Reserved ICUT2[2] ICUT4[2] Reserved Reserved Reserved CLC_EN HP[1] Reserved Reserved Reserved Reserved Reserved ICUT2[1] ICUT4[1] Reserved Reserved Reserved DET_BY HP[0] Reserved Reserved Reserved Reserved Reserved ICUT2[0] ICUT4[0] Reserved Reserved Reserved OSCF_RS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AC_TH[2] Reserved Reserved Reserved Reserved Reserved Reserved ICUT1[2] ICUT3[2] Reserved Reserved Reserved AC_TH[1] Reserved Reserved Reserved Reserved Reserved IVEE[1] ICUT1[1] ICUT3[1] Reserved Reserved Reserved AC_TH[0] Reserved Reserved Reserved Reserved Reserved IVEE[0] ICUT1[0] ICUT[30] -- -- -- 0000,0000 0000,0000 0000,0000 0000,0000 -- -- 0000,0000 0000,0000 0000,0000
MAX5965A/MAX5965B
ICUT Registers 1 and 2 R/W ICUT Registers 3 and 4 R/W
CLASSIFICATION STATUS REGISTERS 2Ch 2Dh 2Eh 2Fh Port 1 Class Port 2 Class Port 3 Class Port 4 Class RO RO RO RO 1 2 3 4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CLASS1[5] CLASS2[5] CLASS3[5] CLASS4[5] CLASS1[4] CLASS2[4] CLASS3[4] CLASS4[4] CLASS1[3] CLASS2[3] CLASS3[3] CLASS4[3] CLASS1[2] CLASS2[2] CLASS3[2] CLASS4[2] CLASS1[1] CLASS2[1] CLASS3[1] CLASS4[1] CLASS1[0] CLASS2[0] CLASS3[0] CLASS4[0] 0000,0000 0000,0000 0000,0000 0000,0000
CURRENT REGISTER 30h 31h 32h 33h 34h 35h 36h 37h Current Port 1 (MSB) Current Port 1 (LSB) Current Port 2 (MSB) Current Port 2 (LSB) Current Port 3 (MSB) Current Port 3 (LSB) Current Port 4 (MSB) Current Port 4 (LSB) RO RO RO RO RO RO RO RO 1 1 2 2 3 3 4 4 IPD1[8] Reserved IPD2[8] Reserved IPD3[8] Reserved IPD4[8] Reserved IPD1[7] Reserved IPD2[7] Reserved IPD3[7] Reserved IPD4[7] Reserved IPD1[6] Reserved IPD2[6] Reserved IPD3[6] Reserved IPD4[6] Reserved IPD1[5] Reserved IPD2[5] Reserved IPD3[5] Reserved IPD4[5] Reserved IPD1[4] Reserved IPD2[4] Reserved IPD3[4] Reserved IPD4[4] Reserved IPD1[3] Reserved IPD2[3] Reserved IPD3[3] Reserved IPD4[3] Reserved IPD1[2] Reserved IPD2[2] Reserved IPD3[2] Reserved IPD4[2] Reserved IPD1[1] IPD1[0] IPD2[1] IPD2[0] IPD3[1] IPD3[0] IPD4[1] IPD4[0] 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000
*UV and UVLO bits of VEE and VDD asserted depends on the order VEE and VDD supplies are brought up. A = AUTO pin state before reset. M = MIDSPAN state before reset. A3...0 = ADDRESS input states before reset.
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45
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Applications Information
RJ-45 CONNECTOR 1 3 PHY RD1+ RD1RX1+ RX124 22 1 2 3 6 -48VOUT 0.1F RXT1 23 75 1000pF 250VAC 75 75 75 0.1F 4 5 0.1F TXCT1 20 0.1F 7 8
1/2 OF 21 H2005A TX1+ 4 TD1+* 19 TX15 TD1-
-48VRTN VCC (3.3V) ISOLATION 1.8V TO 5V, (REF TO DGND) 3k 180 VDD VDD
AGND
A0
A1
A2
A3
RESET
1k
HPCL063L VCCRTN
3k INT SDAOUT
INTERNAL 50k PULLUP
4.7k
SERIAL INTERFACE
OPTIONAL BUFFER 180
3k SDAIN
AUTO MIDSPAN
INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) SINE WAVE 100Hz 10% PEAK AMPLITUDE 2.2V 0.1V VALLEY AMPLITUDE 0.2V 0.1V
SDA OPTIONAL BUFFER 180
HPCL063L
MAX5965A MAX5965B
OSC_IN
3k SCL HPCL063L SHD_ OFF
ON
SCL OPTIONAL BUFFER DGND
VEE
0.5 1%
SENSE_ GATE_
OUT_
DET_
1k 0.47F 100V SMBJ 58CA 0.1F 2.2M -48VOUT
100
1N4448
-48V 1N4002 FDT3612 100V, 120m SOT-223 *USE HALO TG111-HRPE40NY OR PULSE HX6015NL FOR HIGH POWER
1 OF 4 CHANNELS
Figure 13. PoE System Block Diagram
46
______________________________________________________________________________________
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
RJ-45 CONNECTOR 1 2 DATA 3 6
4 5 7 -48VOUT 8
-48VRTN VCC (3.3V) ISOLATION 1.8V TO 5V (REF TO DGND) 3k 180 VDD VDD
AGND
A0
A1
A2
A3
RESET
1k
HPCL063L VCCRTN
3k INT SDAOUT
INTERNAL 50k PULLUP
4.7k
SERIAL INTERFACE
OPTIONAL BUFFER 180
3k SDAIN
AUTO MIDSPAN
INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) SINE WAVE 100Hz 10% PEAK AMPLITUDE 2.2V 0.1V VALLEY AMPLITUDE 0.2V 0.1V
SDA OPTIONAL BUFFER 180
HPCL063L
MAX5965A MAX5965B
OSC_IN
3k SCL HPCL063L SHD_ OFF
ON
SCL OPTIONAL BUFFER DGND
VEE
0.5 1%
SENSE_ GATE_
OUT_
DET_
1k 0.47F 100V SMBJ 58CA 0.1F 2.2M -48VOUT
100
1N4448
-48V 1N4002 FDT3612 100V, 120m SOT-223
1 OF 4 CHANNELS
Figure 14. PoE System Block Diagram
______________________________________________________________________________________
47
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
R10 2 R6 1 C3 15nF R5 1k Q4 MMBTA56 DRAIN 1 2 C6 0.47F 100V 3 4 V+ VDD FB SS_SHDN C4 220F Sanyo 6SVPA220MAA L1 68H, DO3308P-683 D1 DIODES INC.: B1100 R1 2.61k
+3.3V
+3.3V
300mA C5 4.7F
GND GND
Q2 MMBTA56 GND
MAX5020
VCC NDRV GND CS
8 7 6 5
R8 30
GATE SOURCE
Q1 Si2328 DS C9 4.7nF C7 0.22F
Q3 MMBTA56
C2 0.022F -48V -48V
C1 0.1F
C8 2.2F
R4 1
R9 1
R2 6.81k R7 1.02k
R3 2.61k
Figure 15. -48V to +3.3V (300mA) Boost Converter Solution for VDIG
1700 (mils)
1700 (mils)
1700 (mils)
965 (mils)
965 (mils)
Figure 16. Layout Example for Boost Converter Solution for VDIG
48
______________________________________________________________________________________
965 (mils)
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Component List for VDIG Supply
DESIGNATION C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 L1 DESCRIPTION 0.1F, 25V ceramic capacitor 0.022F, 25V ceramic capacitor 15nF, 25V ceramic capacitor 220F capacitor Sanyo 6SVPA220MAA 4.7F, 16V ceramic capacitor 0.47F, 100V ceramic capacitor 0.22F, 16V ceramic capacitor 2.2F, 16V ceramic capacitor 4.7nF, 16V ceramic capacitor B1100 100V Schottky diode 68H inductor Coilcraft DO3308P-683 or equivalent DESIGNATION Q1 Q2, Q3, Q4 R1, R3 R2 R4, R6, R9 R5 R7 R8 R10 U1 DESCRIPTION Si2328DS Vishay n-channel MOSFET, SOT23 MMBTA56 small-signal PNP 2.61k 1% resistors 6.81k 1% resistor 1 1% resistors 1k 1% resistor 1.02k 1% resistor 30 1% resistor 2 1% resistor High-voltage PWM IC MAX5020ESA (8-pin SO)
MAX5965A/MAX5965B
Pin Configuration
TOP VIEW
RESET 1 MIDSPAN 2
+
36 OSC 35 AUTO 34 OUT1 33 GATE1 32 SENSE1
INT 3 SCL SDAOUT SDAIN A3 A2 A1 4 5 6 7 8 9
MAX5965A MAX5965B
31 OUT2 30 GATE2 29 SENSE2 28 VEE 27 OUT3 26 GATE3 25 SENSE3 24 OUT4 23 GATE4 22 SENSE4 21 AGND 20 SHD4 19 SHD3
A0 10 DET1 11 DET2 12 DET3 13 DET4 14 DGND 15 VDD 16 SHD1 17 SHD2 18
SSOP ______________________________________________________________________________________ 49
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Typical Operating Circuits
-48VRTN VCC (3.3V) ISOLATION 1.8V TO 3.7V, (REF TO DGND) 3k 180 VDD -48V RTN OUTPUT TO PORT VDD
AGND
A0
A1
A2
A3
1k
3k VCCRTN SDAOUT OPTIONAL BUFFER 3k
RESET INTERNAL 50k PULLUP INT AUTO SDAIN INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) N.C. 4.7k
SERIAL INTERFACE
HPCL063L 180
SDA OPTIONAL BUFFER 180
HPCL063L
MAX5965A MAX5965B
MIDSPAN OSC_IN
3k SCL HPCL063L
SHD_ OFF
ON
SCL OPTIONAL BUFFER DGND
VEE
0.5 1%
SENSE_ GATE_
OUT_
DET_
1N4448 -48V OUTPUT TO PORT
100
-48V FDT3612 100V, 120m SOT-223 NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND. DGND RANGE IS BETWEEN VEE AND (AGND + 4V). 1 OF 4 CHANNELS CAN BE UP TO 100k
Typical Operating Circuit 1 (without AC Load Removal Detection)
50
______________________________________________________________________________________
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet
Typical Operating Circuits (continued)
-48VRTN VCC (3.3V) ISOLATION 1.8V TO 3.7V, (REF TO DGND) 3k 180 VDD -48V RTN OUTPUT TO PORT VDD
MAX5965A/MAX5965B
AGND
A0
A1
A2
A3
1k
3k VCCRTN SDAOUT OPTIONAL BUFFER 3k
RESET INTERNAL 50k PULLUP INT AUTO SDAIN INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) N.C. 4.7k
SERIAL INTERFACE
HPCL063L 180
SDA OPTIONAL BUFFER 180
HPCL063L
MAX5965A MAX5965B
MIDSPAN OSC_IN
3k SCL HPCL063L
SHD_ OFF
ON
SCL OPTIONAL BUFFER DGND
VEE
0.5 1%
SENSE_ GATE_
OUT_
DET_
1N4448 -48V OUTPUT TO PORT
100
-48V FDT3612 100V, 120m SOT-223 NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND. DGND RANGE IS BETWEEN VEE AND (AGND + 4V). 1 OF 4 CHANNELS CAN BE UP TO 100k
Typical Operating Circuit 2 (without AC Load Removal Detection); Alternative DGND Connection
______________________________________________________________________________________
51
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B
Typical Operating Circuits (continued)
-48V RTN OUTPUT TO PORT
-48VRTN VCC (3.3V) ISOLATION 1.8V TO 3.7V, (REF TO DGND) 3k 180 VDD
VDD
AGND
A0
A1
A2
A3
RESET
1k
HPCL063L VCCRTN
3k INT SDAOUT
INTERNAL 50k PULLUP
4.7k
SERIAL INTERFACE
OPTIONAL BUFFER 180
3k SDAIN
AUTO MIDSPAN
INTERNAL PULLDOWN (MANUAL MODE) INTERNAL PULLDOWN (SIGNAL MODE) SINE WAVE 100Hz 10% PEAK AMPLITUDE 2.2V 0.1V VALLEY AMPLITUDE 0.2V 0.1V
SDA OPTIONAL BUFFER 180
HPCL063L
MAX5965B
OSC_IN
3k SCL HPCL063L SHD_ OFF
ON
SCL OPTIONAL BUFFER DGND
VEE
0.5 1%
SENSE_ GATE_
OUT_
DET_
1k 0.47F 100V -48V OUTPUT TO PORT
100
1N4448
-48V 1N4002 FDT3612 100V, 120m SOT-223 CAN BE UP TO 100k 1 OF 4 CHANNELS
NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND. DGND MUST BE CONNECTED DIRECTLY TO AGND FOR AC DISCONNECT DETECTION CIRCUIT TO OPERATE.
Typical Operating Circuit 3 (with AC Load Removal Detection)
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 36 SSOP PACKAGE CODE A36-4 DOCUMENT NO. 21-0040
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
52 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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